Attention is currently required from: Anil Kumar K, Subrata Banik, Jérémy Compostella, Tim Wawrzynczak. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63750 )
Change subject: soc/intel/common: Add Raptor Lake device IDs ......................................................................
Patch Set 2:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63750/comment/5e8eba96_9aed0333 PS1, Line 9: Add Raptor Lake specific CPU, System Agent, PCH,
The line break is unnecessary as the line length is 64 characters. […]
Done
File src/include/cpu/intel/cpu_ids.h:
https://review.coreboot.org/c/coreboot/+/63750/comment/ed3a989e_55a27bf5 PS1, Line 62: #define CPUID_RAPTORLAKE_J0 0xb06a2
According the EDS section 15.0, there are two SKUs (P and S) with two different CPUIDs. […]
I followed the naming convention but CPUID_RAPTORLAKE_P_J0 maybe good idea. I don't think we will need S SKU. Yes, J0 stepping.
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/63750/comment/4761fffc_0b5e71cd PS1, Line 3079: #define PCI_DID_INTEL_RPL_P_ESPI_1 0x519d
Where does this second eSPI MC comes from ? I don't find it in the PCH EDS.
Documents are missing some of the device-ids, they are being updated.
https://review.coreboot.org/c/coreboot/+/63750/comment/6c456e5a_6dd0295b PS1, Line 4149: #define PCI_DID_INTEL_RPL_TCSS_XHCI 0xa71e
Where is it defined? I could not find it.
Documents are missing some of the device-ids, they are being updated.
https://review.coreboot.org/c/coreboot/+/63750/comment/6745aca4_44bb37fb PS1, Line 4350: #define PCI_DID_INTEL_RPL_TBT_RP0 0xa76e
Where are they defined? I could not find them.
Documents are missing some of the device-ids, they are being updated.
https://review.coreboot.org/c/coreboot/+/63750/comment/faabe243_050a6f46 PS1, Line 4394: #define PCI_DID_INTEL_RPL_IPU 0xa75d
Where is it defined? I could not find it.
Documents are missing some of the device-ids, they are being updated.
File src/soc/intel/alderlake/cpu.c:
https://review.coreboot.org/c/coreboot/+/63750/comment/b0af3bb1_e20d564f PS1, Line 262: adl_p_mch_ids
should be rpl_p_mch_ids right ? […]
done. I think we can push func/macro in a separate patch
File src/soc/intel/common/block/dtt/dtt.c:
https://review.coreboot.org/c/coreboot/+/63750/comment/c095866d_aad1f824 PS1, Line 8: PCI_DID_INTEL_RPL_DTT,
Is there any reason why it is being added at the beginning ?
faster boot time?