Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51068 )
Change subject: sb/intel/common/pciehp: Replace HP dummy device with common code ......................................................................
sb/intel/common/pciehp: Replace HP dummy device with common code
Use the common PCIEXP_HOTPLUG code to generate a dummy device for PCIe ports supporting hotplug. This allows to have control over how much resources are allocated to hotplug ports.
Tested on thinkpad X220: now hotplugging a dGPU via the expresscard slot sometimes works.
Change-Id: I3eec5214c9d200ef97d1ccfdc00e8ea0ee7cfbc6 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/51068 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Patrick Rudolph --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/common/pciehp.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/pcie.c 7 files changed, 24 insertions(+), 54 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve Angel Pons: Looks good to me, but someone else must approve
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 812b6c0..701c98b 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -65,4 +65,7 @@ device will be hidden when ME is in an inoperable mode, e.g. if me_cleaner was used.
+config PCIEXP_HOTPLUG + default y + endif diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index f6bffbb..8513390 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -244,11 +244,11 @@ { struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
- /* Normal PCIe Scan */ - pciexp_scan_bridge(dev); - - if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { - intel_acpi_pcie_hotplug_scan_slot(dev->link_list); + if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { + pciexp_hotplug_scan_bridge(dev); + } else { + /* Normal PCIe Scan */ + pciexp_scan_bridge(dev); }
/* Late Power Management init after bridge device enumeration */ diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c index 247bf5d..31fbb21 100644 --- a/src/southbridge/intel/common/pciehp.c +++ b/src/southbridge/intel/common/pciehp.c @@ -117,42 +117,3 @@ acpigen_pop_len();
} - -static void slot_dev_read_resources(struct device *dev) -{ - struct resource *resource; - - resource = new_resource(dev, PCI_BASE_ADDRESS_0); - resource->size = 1 << 23; - resource->align = 22; - resource->gran = 22; - resource->limit = 0xffffffff; - resource->flags |= IORESOURCE_MEM; - - resource = new_resource(dev, 0x14); - resource->size = 1 << 23; - resource->align = 22; - resource->gran = 22; - resource->limit = 0xffffffff; - resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; - - resource = new_resource(dev, 0x18); - resource->size = 1 << 12; - resource->align = 12; - resource->gran = 12; - resource->limit = 0xffff; - resource->flags |= IORESOURCE_IO; -} - -static struct device_operations slot_dev_ops = { - .read_resources = slot_dev_read_resources, -}; - -/* Add a dummy device to reserve I/O space for hotpluggable devices. */ -void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus) -{ - struct device *slot; - struct device_path slot_path = { .type = DEVICE_PATH_NONE }; - slot = alloc_dev(bus, &slot_path); - slot->ops = &slot_dev_ops; -} diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 3ee2943..992562f 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -38,4 +38,7 @@ bool default n
+config PCIEXP_HOTPLUG + default y + endif diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index 3900e92..a20e7d6 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -63,11 +63,11 @@ { struct southbridge_intel_i82801ix_config *config = dev->chip_info;
- /* Normal PCIe Scan */ - pciexp_scan_bridge(dev); - - if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { - intel_acpi_pcie_hotplug_scan_slot(dev->link_list); + if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { + pciexp_hotplug_scan_bridge(dev); + } else { + /* Normal PCIe Scan */ + pciexp_scan_bridge(dev); } }
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 687cb45..fa469ce 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -39,4 +39,7 @@ bool default n
+config PCIEXP_HOTPLUG + default y + endif diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index 18d2c72..133d502 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -63,11 +63,11 @@ { struct southbridge_intel_i82801jx_config *config = dev->chip_info;
- /* Normal PCIe Scan */ - pciexp_scan_bridge(dev); - - if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { - intel_acpi_pcie_hotplug_scan_slot(dev->link_list); + if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { + pciexp_hotplug_scan_bridge(dev); + } else { + /* Normal PCIe Scan */ + pciexp_scan_bridge(dev); } }