Attention is currently required from: Matt DeVillier, Sean Rhodes.
Subrata Banik has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/85696?usp=email )
Change subject: intel/common/rtd3: Allow emitting PSD0 Method for PCH Root Ports ......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/common/block/pcie/rtd3/rtd3.c:
https://review.coreboot.org/c/coreboot/+/85696/comment/2101ce50_88e81f0c?usp... : PS5, Line 437: if (rp_type != PCIE_RP_PCH) {
Modphy gatting is supported only for PCIe root port under PCH in rtd3.c. The CPU PCIe root ports in older archecture like Tiger Lake Alder lake do not have this support. However, In the recent SoC architecture, all PCIe Root ports in PCD (i.e. PCIE_RP_PCH) and therefore, modPHY gating is supported for all RP ports. Please see src/soc/intel/common/block/pcie/rtd3/chip.h for the comments regarding of ext_pm_support.
Thanks Cliff for taking look into this. We should introduce a newer Kconfig for CPU RPs to enable this feature and let applicable SoC to select that Kconfig (rather enabling RTD3 control for CPU Rps like what this CL initially attempted)