[coreboot-gerrit] Change in coreboot[master]: src/mb/intel/coffeelake_rvp: Enable LAN clock source usage for Jackso...

[Raymond Chung (Code Review)]

Raymond Chung has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38675 )

Change subject: src/mb/intel/coffeelake_rvp: Enable LAN clock source usage for Jacksonville LOM GbE
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src/mb/intel/coffeelake_rvp: Enable LAN clock source usage for Jacksonville LOM GbE

FSP defined a special clock source usage 0x70 for PCH LAN device, update that to intel coffeelake_rvp cml_s platform.

TEST=Boot up into OS, ethernet able to be listed in ifconfig.

Change-Id: I67399b88520f1371400f0dcd414ac2bcbc51082e
Signed-off-by: raymondchung 
---
M src/mainboard/intel/coffeelake_rvp/variants/cml_s/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/38675/1

diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_s/overridetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/overridetree.cb
index 8ffee7c..aaf1230 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cml_s/overridetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_s/overridetree.cb
@@ -102,7 +102,7 @@
    # PCIe root port 13 for GBe LAN
    register "PcieRpEnable[12]" = "1"
    # RP 13 uses CLK SRC 1
-	register "PcieClkSrcUsage[1]" = "12"
+	register "PcieClkSrcUsage[1]" = "PCIE_CLK_LAN"
    # ClkReq-to-ClkSrc mapping for CLK SRC 1
    register "PcieClkSrcClkReq[1]" = "1"