[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Add `GPE0_STS_BIT` macro

[Furquan Shaikh (Code Review)]

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Angel Pons, Andrey Petrov, Patrick Rudolph.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50916 )

Change subject: soc/intel/apollolake: Add `GPE0_STS_BIT` macro
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Patch Set 1:

(1 comment)

File src/soc/intel/apollolake/include/soc/pm.h:

https://review.coreboot.org/c/coreboot/+/50916/comment/eba673c1_9aa61b73 
PS1, Line 111: GPE0_STS_BIT
> Good point. How would you word such a comment? I'm not too inspired today...

Not the best at it, but I can give it a try :P:

```

/*
 * Datasheet says this bit is reserved. However, `southbridge_smi_handler` uses 
 * GPE0_STS_BIT to ignore GPE0-related SMI events in SCI mode (CB:50750). Though the 
 * bit is reserved for APL/GLK, use of this bit in `southbridge_smi_handler` does not
 * cause any side-effects as the function just masks out this bit in the value read
 * from SMI_STS register. Do not use this bit in any other common code as it can have
 * undefined value for ALK/GLK.
 */
```

And obviously, it is very easy to still miss out on the comment :).