Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/58222 )
Change subject: cpu/intel/haswell: Lock PKG_CST_CONFIG_CONTROL MSR ......................................................................
cpu/intel/haswell: Lock PKG_CST_CONFIG_CONTROL MSR
Set PKG_CST_CONFIG_CONTROL MSR bit 15 to make bits 15:0 read-only.
Change-Id: Ieb740aa94255cb3c23a56495c4b645d847637b7f Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/58222 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@mailbox.org Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Patrick Rudolph: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 2c6384c..90db95b 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -395,6 +395,7 @@ msr.lo |= (1 << 27); // C3 Auto Undemotion Enable msr.lo |= (1 << 26); // C1 Auto Demotion Enable msr.lo |= (1 << 25); // C3 Auto Demotion Enable + msr.lo |= (1 << 15); // Lock bits 15:0 msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection
if (timed_mwait_capable)
1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.