Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35765 )
Change subject: kontron/986lcd-m,roda/rk886ex: Drop secondary PCI reset ......................................................................
kontron/986lcd-m,roda/rk886ex: Drop secondary PCI reset
The extra PCI bus RST# and 200ms delay there was workaround for custom add-on hardware.
Change-Id: I38c4677cfb41d620498be8e0c257b517995bad5c Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35765 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/i945/early_init.c M src/southbridge/intel/i82801gx/i82801gx.h 4 files changed, 0 insertions(+), 17 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index c0e6071..7fa1b42 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -245,9 +245,6 @@
enable_lapic();
- /* Force PCIRST# to conventional PCI slot and Firewire. */ - ich7_p2p_secondary_reset(); - ich7_enable_lpc(); early_superio_config_w83627thg();
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 7949b69..f550632 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -208,9 +208,6 @@
enable_lapic();
- /* Force PCIRST# to cardbus add-on. */ - ich7_p2p_secondary_reset(); - ich7_enable_lpc(); early_superio_config();
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 7ed58f6..ee10fdc 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -17,7 +17,6 @@ #include <cf9_reset.h> #include <console/console.h> #include <arch/io.h> -#include <delay.h> #include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -869,14 +868,6 @@ pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); }
-void ich7_p2p_secondary_reset(void) -{ - pci_devfn_t p2p_bridge = PCI_DEV(0, 0x1e, 0); - pci_s_assert_secondary_reset(p2p_bridge); - mdelay(200); - pci_s_deassert_secondary_reset(p2p_bridge); -} - void i945_early_initialization(void) { /* Print some chipset specific information */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index fec8919..d615b40 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -39,8 +39,6 @@ void i82801gx_enable(struct device *dev); #endif
-void ich7_p2p_secondary_reset(void); - void enable_smbus(void);
#if ENV_ROMSTAGE