Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41609 )
Change subject: soc/intel/denverton_ns/bootblock: Fix 32-bit RW PCI_BASE_ADDRESS_0 register ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/c/coreboot/+/41609/1/src/soc/intel/denverton_ns/... File src/soc/intel/denverton_ns/bootblock/uart.c:
https://review.coreboot.org/c/coreboot/+/41609/1/src/soc/intel/denverton_ns/... PS1, Line 27: mmio_base Why is this called `mmio` if we configure I/O ports?
https://review.coreboot.org/c/coreboot/+/41609/1/src/soc/intel/denverton_ns/... PS1, Line 28: pci_write_config16(uart_dev, PCI_BASE_ADDRESS_0, reg16); Why is this a read-modify-write?
https://review.coreboot.org/c/coreboot/+/41609/1/src/soc/intel/denverton_ns/... PS1, Line 37: allow to initiate : * a transaction as a master Why?
https://review.coreboot.org/c/coreboot/+/41609/1/src/soc/intel/denverton_ns/... PS1, Line 169: early_config_gpio(); Why do we unconditionally change pad configurations?