Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33146
Change subject: Documentation: How to run coreboot on PC Engines APU2 ......................................................................
Documentation: How to run coreboot on PC Engines APU2
There is no documentation about running coreboot on apu2 platform, so now it describes how to do this.
Change-Id: Id1d553c7f7485358960d92e714d50ba0f75b3581 Signed-off-by: Piotr Kleinschmidt piotr.kleinschmidt@3mdeb.com --- A Documentation/mainboard/pcengines/apu2.jpg A Documentation/mainboard/pcengines/apu2.md A Documentation/mainboard/pcengines/apu2_spi.jpg 3 files changed, 110 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33146/1
diff --git a/Documentation/mainboard/pcengines/apu2.jpg b/Documentation/mainboard/pcengines/apu2.jpg new file mode 100644 index 0000000..d221857 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2.jpg Binary files differ diff --git a/Documentation/mainboard/pcengines/apu2.md b/Documentation/mainboard/pcengines/apu2.md new file mode 100644 index 0000000..a8aa3d2 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2.md @@ -0,0 +1,110 @@ +# PC Engines APU2 + +This page describes how to run coreboot on PC Engines APU2 platform. + +## Technology + +```eval_rst ++------------+---------------------------------------------------------------+ +| CPU | AMD G series GX-412TC | ++------------+---------------------------------------------------------------+ +| CPU core | 1 GHz quad Jaguar core with 64 bit support | +| | 32K data + 32K instruction cache per core, shared 2MB L2 cache| ++------------+---------------------------------------------------------------+ +| DRAM | 2 or 4 GB DDR3-1333 DRAM | ++------------+---------------------------------------------------------------+ +| Boot | From SD card, USB, mSATA SSD, SATA | ++------------+---------------------------------------------------------------+ +| Power | 6 to 12W of 12V power | ++------------+---------------------------------------------------------------+ +| Firmware | coreboot with support for iPXE and USB boot | ++------------+---------------------------------------------------------------+ +``` + +## Required proprietary blobs + +To build working coreboot image some blobs are needed. + +```eval_rst ++-----------------+---------------------------------+---------------------+ +| Binary file | Apply | Required / Optional | ++=====================+=============================+=====================+ +| AmdPubKey.bin | AMD Platform Security Processor | Required | ++-----------------+---------------------------------+---------------------+ +| AGESA.bin | AGESA Platform Initialization | Required | ++-----------------+---------------------------------+---------------------+ +| xhci.bin | AMD XHCI controller | Optional | ++-----------------+---------------------------------+---------------------+ +``` + +## Flashing coreboot + +```eval_rst ++---------------------+--------------------------+ +| Type | Value | ++=====================+==========================+ +| Socketed flash | no | ++---------------------+--------------------------+ +| Model | MX25L1606E | ++---------------------+--------------------------+ +| Size | 2 MiB | ++---------------------+--------------------------+ +| Package | SOP-8 | ++---------------------+--------------------------+ +| Write protection | jumper on WP# pin | ++---------------------+--------------------------+ +| Dual BIOS feature | no | ++---------------------+--------------------------+ +| Internal flashing | Super IO Nuvoton NCT5104D| ++---------------------+--------------------------+ +``` + +### Internal programming + +The SPI flash can be accessed using [flashrom]. It is important to execute +command with a `-c <chipname>` argument: + + flashrom -p internal -c "MX25L1606E" -w coreboot.rom + +### External programming + +**IMPORTANT**: When programming SPI flash, first you need to enter apu2 in S5 +(Soft-off) power state. S5 state can be forced by shorting power button pin on +J2 header. + +The external access to flash chip is available through standard SOP-8 clip or +SOP-8 header next to the flash chip on the board. Notice that not all boards +have a header soldered down originally. Hence, there could be an empty slot with +8 eyelets, so you can solder down a header on your own. The SPI flash chip and +SPI header are marked in the picture below. Also there is SPI header and SPI +flash pin layout included. + +There is no restrictions as to the programmer device. It is only recommended to +flash firmware without supplying power. External programming can be performed, +for example using OrangePi and Armbian. You can exploit linux_spi driver which +provide communication with SPI devices. Example command to program SPI flash +with OrangePi using linux_spi: + + flashrom -f -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 + + +**apu2 platform with marked in SPI header and SPI flash chip** + +![][apu2_flash] + +**SPI header pin layout** + +![][spi_header] + + +## Schematics + +PC Engines APU2 platform schematics are available for free on PC Engines +official site. Depending on the configuration: +- [apu2b](https://www.pcengines.ch/schema/apu2b.pdf) +- [apu2c](https://www.pcengines.ch/schema/apu2c.pdf) +- [apu2d](https://www.pcengines.ch/schema/apu2d.pdf) + +[apu2_flash]: apu2.jpg +[spi_header]: apu2_spi.jpg +[flashrom]: https://flashrom.org/Flashrom diff --git a/Documentation/mainboard/pcengines/apu2_spi.jpg b/Documentation/mainboard/pcengines/apu2_spi.jpg new file mode 100644 index 0000000..f8a5b58 --- /dev/null +++ b/Documentation/mainboard/pcengines/apu2_spi.jpg Binary files differ