[coreboot-gerrit] [S] Change in coreboot[main]: sb/intel/bd82x6x: Improve SLCAP

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78228?usp=email )

Change subject: sb/intel/bd82x6x: Improve SLCAP
......................................................................

sb/intel/bd82x6x: Improve SLCAP

- Set the 'Hotplug Capable' bit and 'Hot Plug Surprise' bit in SLCAP
  for hotplugable PCIe slots.
- Assign unique slot number.

Test: System still boots and all PCIe devices are working.

Change-Id: I03aeb0a1ff0041901acc20fe700d3f7995d22366
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/pch.h
M src/southbridge/intel/bd82x6x/pcie.c
2 files changed, 9 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/78228/1

diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 727204f..44c723d 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -87,6 +87,7 @@
 # define SI			(1 << 8)
 #define D28Fx_LCTL		0x50
 # define LD			(1 << 4)
+#define D28Fx_SLCAP		0x54
 #define D28Fx_SLSTS		0x58
 # define PDS			(1 << 22)

diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 206894d..59ef2cb 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -43,6 +43,7 @@
 {
    u16 link_width_p0, link_width_p4;
    u8 slot_power_limit = 10; /* 10W for x1 */
+	static u8 slot_number;
    u32 reg32;
    u8 reg8;

@@ -137,11 +138,16 @@
    pci_write_config32(dev, 0x4c, reg32);

/* Set slot power limit as configured above */
-	reg32 = pci_read_config32(dev, 0x54);
+	reg32 = pci_read_config32(dev, D28Fx_SLCAP);
+	reg32 &= ~(3 << 5);
+	if (pci_is_hotplugable(dev))
+		reg32 |= (3 << 5);
    reg32 &= ~((1 << 15) | (1 << 16)); /* 16:15 = Slot power scale */
    reg32 &= ~(0xff << 7);             /* 14:7  = Slot power limit */
    reg32 |= (slot_power_limit << 7);
-	pci_write_config32(dev, 0x54, reg32);
+	reg32 &= ~(0x1fff << 19);
+	reg32 |= (slot_number++ << 19);
+	pci_write_config32(dev, D28Fx_SLCAP, reg32);
 }

static void pch_pcie_pm_late(struct device *dev)