Philipp Hug has posted comments on this change. ( https://review.coreboot.org/29024 )
Change subject: riscv: add support to block smp in each stage ......................................................................
Patch Set 11:
(6 comments)
Thanks!
https://review.coreboot.org/#/c/29024/11/src/arch/riscv/boot.c File src/arch/riscv/boot.c:
https://review.coreboot.org/#/c/29024/11/src/arch/riscv/boot.c@31 PS11, Line 31: static void arch_prog_run_help(struct prog *prog) suggestion: rename to do_arch_prog_run()
https://review.coreboot.org/#/c/29024/11/src/arch/riscv/stages.c File src/arch/riscv/stages.c:
https://review.coreboot.org/#/c/29024/11/src/arch/riscv/stages.c@35 PS11, Line 35: smp_pause(); this will only be reached by harts!=0 in romstage as the others are paused already in bootblock.s and romstage.s
Can we make this more consistent?
https://review.coreboot.org/#/c/29024/11/src/soc/sifive/fu540/Kconfig File src/soc/sifive/fu540/Kconfig:
https://review.coreboot.org/#/c/29024/11/src/soc/sifive/fu540/Kconfig@42 PS11, Line 42: config RISCV_HART_NUM This should probably be done in 29023
https://review.coreboot.org/#/c/29024/11/src/soc/sifive/fu540/Makefile.inc File src/soc/sifive/fu540/Makefile.inc:
https://review.coreboot.org/#/c/29024/11/src/soc/sifive/fu540/Makefile.inc@2... PS11, Line 22: romstage-y += clint.c This should probably be done in 29023
https://review.coreboot.org/#/c/29024/11/src/soc/ucb/riscv/Makefile.inc File src/soc/ucb/riscv/Makefile.inc:
https://review.coreboot.org/#/c/29024/11/src/soc/ucb/riscv/Makefile.inc@1 PS11, Line 1: ifeq ($(CONFIG_SOC_UCB_RISCV),y) This should probably be done in 29023
https://review.coreboot.org/#/c/29024/11/src/soc/ucb/riscv/ipi.c File src/soc/ucb/riscv/ipi.c:
https://review.coreboot.org/#/c/29024/11/src/soc/ucb/riscv/ipi.c@1 PS11, Line 1: /* This file should probably be added in change 29023 instead