Dave Frodin (dave.frodin@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10145
-gerrit
commit 4dc8e885dcf0ab6a96ba907dd443d00f25da159b Author: Dave Frodin dave.frodin@se-eng.com Date: Fri May 8 07:24:06 2015 -0600
superio: Use the indexed I/O functions
Replace the multiple indexed I/O read write functions with the generic functions.
Change-Id: Idfe7a8784c28d51b3fbcb2f4e26beaa0b91741a8 Signed-off-by: Dave Frodin dave.frodin@se-eng.com --- src/superio/fintek/f71869ad/f71869ad_hwm.c | 31 +++++++++++++----------------- src/superio/ite/it8716f/superio.c | 16 +++------------ src/superio/ite/it8728f/it8728f_hwm.c | 19 +++++++----------- src/superio/smsc/lpc47b397/superio.c | 21 +++++--------------- src/superio/winbond/w83627ehg/superio.c | 17 +++------------- src/superio/winbond/w83627hf/superio.c | 17 +++------------- 6 files changed, 34 insertions(+), 87 deletions(-)
diff --git a/src/superio/fintek/f71869ad/f71869ad_hwm.c b/src/superio/fintek/f71869ad/f71869ad_hwm.c index 25bc1ff..66fc931 100644 --- a/src/superio/fintek/f71869ad/f71869ad_hwm.c +++ b/src/superio/fintek/f71869ad/f71869ad_hwm.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <io_index.h> #include "chip.h" #include "fintek_internal.h"
@@ -55,12 +56,6 @@ #define HWM_FAN1_SEG3_SPEED_COUNT 0xAC #define HWM_FAN1_TEMP_MAP_SEL 0xAF
-static void pnp_write_index(u16 port, u8 reg, u8 value) -{ - outb(reg, port); - outb(value, port + 1); -} - /* note: multifunc registers need to be tweaked before here */ void f71869ad_hwm_init(struct device *dev) { @@ -84,29 +79,29 @@ void f71869ad_hwm_init(struct device *dev) /* Fintek F71869AD HWM (ordered) programming sequence. */
/* SMBus Address p.53 */ - pnp_write_index(port, HWM_SMBUS_ADDR, conf->hwm_smbus_address); + io_write_index(port, HWM_SMBUS_ADDR, conf->hwm_smbus_address); /* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */ - pnp_write_index(port, HWM_SMBUS_CONTROL_REG, conf->hwm_smbus_control_reg); + io_write_index(port, HWM_SMBUS_CONTROL_REG, conf->hwm_smbus_control_reg); /* Tfan1 = Tnow + (Ta - Tb)*Ct where, */ /* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */ - pnp_write_index(port, HWM_FAN1_TEMP_MAP_SEL, conf->hwm_fan1_temp_map_sel); + io_write_index(port, HWM_FAN1_TEMP_MAP_SEL, conf->hwm_fan1_temp_map_sel); /* set FAN_PROG_SEL = 1 */ - pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x8a); + io_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x8a); /* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL=1, p.64-65 */ - pnp_write_index(port, HWM_FAN_TYPE_SEL_REG, conf->hwm_fan_type_sel_reg); + io_write_index(port, HWM_FAN_TYPE_SEL_REG, conf->hwm_fan_type_sel_reg); /* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */ - pnp_write_index(port, HWM_FAN_MODE_SEL_REG, conf->hwm_fan_mode_sel_reg); + io_write_index(port, HWM_FAN_MODE_SEL_REG, conf->hwm_fan_mode_sel_reg); /* TFAN1_ADJ_{UP,DOWN}_RATE (Ct=1/4 up & down) in 0x95 when FAN_PROG_SEL = 1, p.88 */ - pnp_write_index(port, HWM_FAN1_TEMP_ADJ_RATE_REG, conf->hwm_fan1_temp_adj_rate_reg); + io_write_index(port, HWM_FAN1_TEMP_ADJ_RATE_REG, conf->hwm_fan1_temp_adj_rate_reg); /* set FAN_PROG_SEL = 0 */ - pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x0a); + io_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x0a); /* FAN1 RPM mode p.70 */ - pnp_write_index(port, HWM_FAN1_IDX_RPM_MODE, conf->hwm_fan1_idx_rpm_mode); + io_write_index(port, HWM_FAN1_IDX_RPM_MODE, conf->hwm_fan1_idx_rpm_mode); /* FAN1 Segment X Speed Count */ - pnp_write_index(port, HWM_FAN1_SEG1_SPEED_COUNT, conf->hwm_fan1_seg1_speed_count); - pnp_write_index(port, HWM_FAN1_SEG2_SPEED_COUNT, conf->hwm_fan1_seg2_speed_count); - pnp_write_index(port, HWM_FAN1_SEG3_SPEED_COUNT, conf->hwm_fan1_seg3_speed_count); + io_write_index(port, HWM_FAN1_SEG1_SPEED_COUNT, conf->hwm_fan1_seg1_speed_count); + io_write_index(port, HWM_FAN1_SEG2_SPEED_COUNT, conf->hwm_fan1_seg2_speed_count); + io_write_index(port, HWM_FAN1_SEG3_SPEED_COUNT, conf->hwm_fan1_seg3_speed_count);
pnp_exit_conf_mode(dev); } diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index 56747ba..717f51c 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -24,6 +24,7 @@ #include <device/device.h> #include <device/pnp.h> #include <console/console.h> +#include <io_index.h> #include <pc80/keyboard.h> #include <arch/io.h> #include <stdlib.h> @@ -32,29 +33,18 @@ #include "it8716f.h"
#if !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL -static void pnp_write_index(u16 port_base, u8 reg, u8 value) -{ - outb(reg, port_base); - outb(value, port_base + 1); -} - -static u8 pnp_read_index(u16 port_base, u8 reg) -{ - outb(reg, port_base); - return inb(port_base + 1); -}
static void init_ec(u16 base) { u8 value;
/* Read out current value of FAN_CTL (0x14). */ - value = pnp_read_index(base, 0x14); + value = io_read_index(base, 0x14); printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n", base + 0x14, value);
/* Set FAN_CTL (0x14) polarity to high, activate fans 1, 2 and 3. */ - pnp_write_index(base, 0x14, value | 0x87); + io_write_index(base, 0x14, value | 0x87); printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n", base + 0x14, value | 0x87); } diff --git a/src/superio/ite/it8728f/it8728f_hwm.c b/src/superio/ite/it8728f/it8728f_hwm.c index 23fa9e8..bc17679 100644 --- a/src/superio/ite/it8728f/it8728f_hwm.c +++ b/src/superio/ite/it8728f/it8728f_hwm.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pnp.h> +#include <io_index.h> #include "chip.h" #include "it8728f_internal.h"
@@ -35,12 +36,6 @@ #define HWM_FAN3_CTL_PWM 0x17 /* default 0x00 */ #define HWM_ADC_TEMP_CHAN_EN_REG 0x51 /* default 0x00 */
-static void pnp_write_index(u16 port, u8 reg, u8 value) -{ - outb(reg, port); - outb(value, port + 1); -} - void it8728f_hwm_ec_init(struct device *dev) { struct superio_ite_it8728f_config *conf = dev->chip_info; @@ -64,18 +59,18 @@ void it8728f_hwm_ec_init(struct device *dev) /* ITE IT8728F HWM (ordered) programming sequence. */
/* configure fan polarity */ - pnp_write_index(port, HWM_CTL_REG, conf->hwm_ctl_register); + io_write_index(port, HWM_CTL_REG, conf->hwm_ctl_register);
/* enable fans 1-3 */ - pnp_write_index(port, HWM_MAIN_CTL_REG, conf->hwm_main_ctl_register); + io_write_index(port, HWM_MAIN_CTL_REG, conf->hwm_main_ctl_register);
/* enable termistor temps for temp1-temp3 */ - pnp_write_index(port, HWM_ADC_TEMP_CHAN_EN_REG, conf->hwm_adc_temp_chan_en_reg); + io_write_index(port, HWM_ADC_TEMP_CHAN_EN_REG, conf->hwm_adc_temp_chan_en_reg);
/* configure which fanX uses which tempY */ - pnp_write_index(port, HWM_FAN1_CTL_PWM, conf->hwm_fan1_ctl_pwm); - pnp_write_index(port, HWM_FAN2_CTL_PWM, conf->hwm_fan2_ctl_pwm); - pnp_write_index(port, HWM_FAN3_CTL_PWM, conf->hwm_fan3_ctl_pwm); + io_write_index(port, HWM_FAN1_CTL_PWM, conf->hwm_fan1_ctl_pwm); + io_write_index(port, HWM_FAN2_CTL_PWM, conf->hwm_fan2_ctl_pwm); + io_write_index(port, HWM_FAN3_CTL_PWM, conf->hwm_fan3_ctl_pwm);
pnp_exit_conf_mode(dev); } diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 9c4a3b6..bedc0cf 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -23,6 +23,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <io_index.h> #include <superio/conf_mode.h> #include <console/console.h> #include <device/smbus.h> @@ -31,18 +32,6 @@ #include <stdlib.h> #include "lpc47b397.h"
-static void pnp_write_index(u16 port, u8 reg, u8 value) -{ - outb(reg, port); - outb(value, port + 1); -} - -static u8 pnp_read_index(u16 port, u8 reg) -{ - outb(reg, port); - return inb(port + 1); -} - static void enable_hwm_smbus(struct device *dev) { /* Enable SensorBus register access. */ @@ -109,10 +98,10 @@ static int lsmbus_read_byte(struct device *dev, u8 address)
res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
- pnp_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */ + io_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */
/* We only read it one byte one time. */ - result = pnp_read_index(res->base + SB_INDEX, address); + result = io_read_index(res->base + SB_INDEX, address);
return result; } @@ -125,10 +114,10 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) device = dev->path.i2c.device; res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
- pnp_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */ + io_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */
/* We only write it one byte one time. */ - pnp_write_index(res->base+SB_INDEX, address, val); + io_write_index(res->base+SB_INDEX, address, val);
return 0; } diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 73ab022..2d20203 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <io_index.h> #include <superio/conf_mode.h> #include <console/console.h> #include <string.h> @@ -32,18 +33,6 @@ #include <stdlib.h> #include "w83627ehg.h"
-static void pnp_write_index(u16 port, u8 reg, u8 value) -{ - outb(reg, port); - outb(value, port + 1); -} - -static u8 pnp_read_index(u16 port, u8 reg) -{ - outb(reg, port); - return inb(port + 1); -} - static void enable_hwm_smbus(struct device *dev) { u8 reg8; @@ -83,12 +72,12 @@ static void init_hwm(u16 base)
for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { reg = hwm_reg_values[i]; - value = pnp_read_index(base, reg); + value = io_read_index(base, reg); value &= 0xff & (~(hwm_reg_values[i + 1])); value |= 0xff & hwm_reg_values[i + 2]; printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, " "value = 0x%02x\n", base, reg, value); - pnp_write_index(base, reg, value); + io_write_index(base, reg, value); } }
diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 2d69fad..c911f49 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> +#include <io_index.h> #include <superio/conf_mode.h> #include <console/console.h> #include <string.h> @@ -32,18 +33,6 @@ #include <stdlib.h> #include "w83627hf.h"
-static void pnp_write_index(u16 port, u8 reg, u8 value) -{ - outb(reg, port); - outb(value, port + 1); -} - -static u8 pnp_read_index(u16 port, u8 reg) -{ - outb(reg, port); - return inb(port + 1); -} - static void enable_hwm_smbus(struct device *dev) { u8 reg8; @@ -90,12 +79,12 @@ static void init_hwm(u16 base)
for (i = 0; i < ARRAY_SIZE(hwm_reg_values); i += 3) { reg = hwm_reg_values[i]; - value = pnp_read_index(base, reg); + value = io_read_index(base, reg); value &= 0xff & hwm_reg_values[i + 1]; value |= 0xff & hwm_reg_values[i + 2]; printk(BIOS_DEBUG, "base = 0x%04x, reg = 0x%02x, " "value = 0x%02x\n", base, reg, value); - pnp_write_index(base, reg, value); + io_write_index(base, reg, value); } }