Hello Duan huayang,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/40525
to review the following change.
Change subject: soc/mediatek/mt8183: High frequency should use range 1 [DRAFT] [DONOT MERGE] ......................................................................
soc/mediatek/mt8183: High frequency should use range 1 [DRAFT] [DONOT MERGE]
Update setting of DRS config.
BUG=153614919 BRANCH=kukui TEST=Boots correctly on Kukui
Change-Id: Ie7680b1bf0c29c946d18e3b27626ce6f31c4216b Signed-off-by: Huayang Duan huayang.duan@mediatek.com --- M src/soc/mediatek/mt8183/dramc_init_setting.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 3 files changed, 23 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40525/1
diff --git a/src/soc/mediatek/mt8183/dramc_init_setting.c b/src/soc/mediatek/mt8183/dramc_init_setting.c index 9eebfe8..f452a44 100644 --- a/src/soc/mediatek/mt8183/dramc_init_setting.c +++ b/src/soc/mediatek/mt8183/dramc_init_setting.c @@ -1219,8 +1219,8 @@ (0x7 << 0) | (0x7 << 4) | (0x7 << 8) | (0x7 << 12) | (0x7 << 16) | (0x7 << 20) | (0x7 << 24) | (0x7 << 28)); clrbits32(&ch[0].ao.shu[0].selph_ca5, 0x7 << 8); - clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0); - clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs0, 0x77777777, SELPH_DQS0_3200); + clrsetbits32(&ch[0].ao.shu[0].selph_dqs1, 0x77777777, SELPH_DQS1_3200);
for (size_t rank = 0; rank < 2; rank++) { clrsetbits32(&ch[0].ao.shu[0].rk[rank].selph_dq[0], diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 024c039..ae14480 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -221,9 +221,7 @@ { dramc_auto_refresh_switch(chn, false);
- if (rank == RANK_0 && (freq_group == LP4X_DDR3600 || - freq_group == LP4X_DDR1600 || - freq_group == LP4X_DDR2400)) + if (rank == RANK_0) write_leveling_move_dqs_instead_of_clk(chn);
SET32_BITFIELDS(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], @@ -245,9 +243,11 @@ }
static void dramc_cmd_bus_training(u8 chn, u8 rank, u8 freq_group, - const struct sdram_params *params, const bool fast_calib) + const struct sdram_params *params, const bool fast_calib, + struct mr_value *mr) { u32 final_vref, clk_dly, cmd_dly, cs_dly; + u8 fsp = get_freq_fsq(freq_group);
clk_dly = params->cbt_clk_dly[chn][rank]; cmd_dly = params->cbt_cmd_dly[chn][rank]; @@ -267,7 +267,15 @@ SHU1_R0_CA_CMD9_RG_RK0_ARPI_CS, cs_dly);
/* CBT set vref */ - dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref); + if (fsp == FSP_0) { + mr->MR13Value &= ~(1<<6); + mr->MR13Value &= 0x7f; + } else { + mr->MR13Value |= (1<<6); + mr->MR13Value |= 0x80; + } + dramc_mode_reg_write_by_rank(chn, rank, 13, mr->MR13Value); + dramc_mode_reg_write_by_rank(chn, rank, 12, final_vref | ( 0x1 << 6)); }
static void dramc_read_dbi_onoff(size_t chn, bool on) @@ -1823,7 +1831,7 @@ vref_end = vref_begin + 1; dramc_dbg("bypass RX vref: %d\n", vref_begin); } else if (type == TX_WIN_DQ_ONLY) { - vref_begin = params->tx_vref[chn][rank]; + vref_begin = params->tx_vref[chn][rank] | (vref_range << 6) ; vref_end = vref_begin + 1; dramc_dbg("bypass TX vref: %d\n", vref_begin); } @@ -2678,7 +2686,7 @@ }
int dramc_calibrate_all_channels(const struct sdram_params *pams, u8 freq_group, - const struct mr_value *mr) + struct mr_value *mr) { bool fast_calib; switch (pams->source) { @@ -2702,7 +2710,7 @@ dramc_dbg("Start K: freq=%d, ch=%d, rank=%d\n", freq_group, chn, rk); dramc_cmd_bus_training(chn, rk, freq_group, pams, - fast_calib); + fast_calib, mr); dramc_write_leveling(chn, rk, freq_group, pams->wr_level); dramc_auto_refresh_switch(chn, true);
diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 19d92b5..e2ca81b 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -10,8 +10,8 @@
#define dramc_err(_x_...) printk(BIOS_ERR, _x_) #define dramc_show(_x_...) printk(BIOS_INFO, _x_) -#if CONFIG(DEBUG_DRAM) -#define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_) +#if 1//IS_ENABLED(CONFIG_DEBUG_DRAM) +#define dramc_dbg(_x_...) printk(BIOS_INFO, _x_) #else #define dramc_dbg(_x_...) #endif @@ -75,12 +75,12 @@ DQ_DIV_MASK = BIT(DQ_DIV_SHIFT) - 1, OEN_SHIFT = 16,
- SELPH_DQS0 = _SELPH_DQS_BITS(0x3, 0x3), - SELPH_DQS1 = _SELPH_DQS_BITS(0x4, 0x1), SELPH_DQS0_1600 = _SELPH_DQS_BITS(0x2, 0x1), SELPH_DQS1_1600 = _SELPH_DQS_BITS(0x1, 0x6), SELPH_DQS0_2400 = _SELPH_DQS_BITS(0x3, 0x2), SELPH_DQS1_2400 = _SELPH_DQS_BITS(0x1, 0x6), + SELPH_DQS0_3200 = _SELPH_DQS_BITS(0x3, 0x3), + SELPH_DQS1_3200 = _SELPH_DQS_BITS(0x5, 0x2), SELPH_DQS0_3600 = _SELPH_DQS_BITS(0x4, 0x3), SELPH_DQS1_3600 = _SELPH_DQS_BITS(0x1, 0x6), }; @@ -99,7 +99,7 @@ void dramc_apply_config_before_calibration(u8 freq_group); void dramc_apply_config_after_calibration(const struct mr_value *mr); int dramc_calibrate_all_channels(const struct sdram_params *pams, - u8 freq_group, const struct mr_value *mr); + u8 freq_group, struct mr_value *mr); void dramc_hw_gating_onoff(u8 chn, bool onoff); void dramc_enable_phy_dcm(u8 chn, bool bEn); void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value);