Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10740
-gerrit
commit 5bc6e5538b816ba1da1a0e0682f0d1d7ace9ffcb Author: Furquan Shaikh furquan@google.com Date: Mon Nov 3 14:39:11 2014 -0800
rk3288: Use timestamp region for pre-cbmem timestamps
BUG=None BRANCH=None TEST=Compiles successfully for veyron_pinky
Original-Change-Id: I3862e9bf2c32085c921adae4c1dcdf88ff0f3ff3 Original-Signed-off-by: Furquan Shaikh furquan@google.com Original-Reviewed-on: https://chromium-review.googlesource.com/227243 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Commit-Queue: Furquan Shaikh furquan@chromium.org Original-Tested-by: Furquan Shaikh furquan@chromium.org
(cherry picked from commit 0fabdbb05826160beb8ee8f89339b18a49e87ab8) Signed-off-by: Marc Jones marc.jones@se-eng.com
Change-Id: I4504d29a43084d4bd406626899b25903200fa6d7 --- src/mainboard/google/veyron_brain/romstage.c | 14 +++----------- src/mainboard/google/veyron_danger/romstage.c | 14 +++----------- src/mainboard/google/veyron_jerry/romstage.c | 14 +++----------- src/mainboard/google/veyron_mickey/romstage.c | 14 +++----------- src/mainboard/google/veyron_mighty/romstage.c | 14 +++----------- src/mainboard/google/veyron_minnie/romstage.c | 14 +++----------- src/mainboard/google/veyron_pinky/romstage.c | 14 +++----------- src/mainboard/google/veyron_rialto/romstage.c | 14 +++----------- src/mainboard/google/veyron_romy/romstage.c | 14 +++----------- src/mainboard/google/veyron_speedy/romstage.c | 14 +++----------- src/soc/rockchip/rk3288/Kconfig | 1 + src/soc/rockchip/rk3288/bootblock.c | 3 +++ src/soc/rockchip/rk3288/include/soc/memlayout.ld | 1 + 13 files changed, 35 insertions(+), 110 deletions(-)
diff --git a/src/mainboard/google/veyron_brain/romstage.c b/src/mainboard/google/veyron_brain/romstage.c index 9f7b1a5..3ea50b6 100644 --- a/src/mainboard/google/veyron_brain/romstage.c +++ b/src/mainboard/google/veyron_brain/romstage.c @@ -80,11 +80,7 @@ static void configure_l2ctlr(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif
console_init(); @@ -94,11 +90,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -110,10 +106,6 @@ void main(void) cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif
diff --git a/src/mainboard/google/veyron_danger/romstage.c b/src/mainboard/google/veyron_danger/romstage.c index 80d9081..0328e95 100644 --- a/src/mainboard/google/veyron_danger/romstage.c +++ b/src/mainboard/google/veyron_danger/romstage.c @@ -81,11 +81,7 @@ static void configure_l2ctlr(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif
console_init(); @@ -98,11 +94,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -114,10 +110,6 @@ void main(void) cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif
diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index e509a4a..06eabe0 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -86,11 +86,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif
console_init(); @@ -103,11 +99,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -119,10 +115,6 @@ void main(void) cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif
diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index 9f7b1a5..3ea50b6 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -80,11 +80,7 @@ static void configure_l2ctlr(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif
console_init(); @@ -94,11 +90,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -110,10 +106,6 @@ void main(void) cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif
diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index e509a4a..06eabe0 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -86,11 +86,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif
console_init(); @@ -103,11 +99,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -119,10 +115,6 @@ void main(void) cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif
diff --git a/src/mainboard/google/veyron_minnie/romstage.c b/src/mainboard/google/veyron_minnie/romstage.c index 68ab661..ffdfdb0 100644 --- a/src/mainboard/google/veyron_minnie/romstage.c +++ b/src/mainboard/google/veyron_minnie/romstage.c @@ -87,11 +87,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif
console_init(); @@ -104,11 +100,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -120,10 +116,6 @@ void main(void) cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif
diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index b536391..5031ad9d 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -94,11 +94,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif
console_init(); @@ -111,11 +107,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -127,10 +123,6 @@ void main(void) cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif
diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index 68ab661..ffdfdb0 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -87,11 +87,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif
console_init(); @@ -104,11 +100,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -120,10 +116,6 @@ void main(void) cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif
diff --git a/src/mainboard/google/veyron_romy/romstage.c b/src/mainboard/google/veyron_romy/romstage.c index 9f7b1a5..3ea50b6 100644 --- a/src/mainboard/google/veyron_romy/romstage.c +++ b/src/mainboard/google/veyron_romy/romstage.c @@ -80,11 +80,7 @@ static void configure_l2ctlr(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif
console_init(); @@ -94,11 +90,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -110,10 +106,6 @@ void main(void) cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif
diff --git a/src/mainboard/google/veyron_speedy/romstage.c b/src/mainboard/google/veyron_speedy/romstage.c index 68ab661..ffdfdb0 100644 --- a/src/mainboard/google/veyron_speedy/romstage.c +++ b/src/mainboard/google/veyron_speedy/romstage.c @@ -87,11 +87,7 @@ static void sdmmc_power_off(void) void main(void) { #if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); + timestamp_add_now(TS_START_ROMSTAGE); #endif
console_init(); @@ -104,11 +100,11 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); #if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); + timestamp_add_now(TS_BEFORE_INITRAM); #endif sdram_init(get_sdram_config()); #if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); + timestamp_add_now(TS_AFTER_INITRAM); #endif
/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ @@ -120,10 +116,6 @@ void main(void) cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 3a4712e..1800b16 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -24,6 +24,7 @@ config SOC_ROCKCHIP_RK3288 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 select ARCH_RAMSTAGE_ARMV7 + select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_MONOTONIC_TIMER select GENERIC_UDELAY select HAVE_UART_SPECIAL diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index d60c860..6ba3230 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -26,9 +26,12 @@ #include <soc/grf.h> #include <soc/timer.h> #include <symbols.h> +#include <timestamp.h>
void bootblock_soc_init(void) { + timestamp_early_init(timestamp_get()); + rkclk_init();
mmu_init(); diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index cd484c8..0b75932 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -41,6 +41,7 @@ SECTIONS OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 41K) TTB_SUBTABLES(0xFF716C00, 1K) PRERAM_CBFS_CACHE(0xFF717000, 1K) + TIMESTAMP(0xFF717400, 0x180) STACK(0xFF717580, 3K - 0x180) SRAM_END(0xFF718000)