[coreboot-gerrit] [M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support

[Subrata Banik (Code Review)]

Attention is currently required from: Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Tarun, Wonkyu Kim.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80275?usp=email )

Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
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Patch Set 16:

(8 comments)

File src/commonlib/include/commonlib/console/post_codes.h:

https://review.coreboot.org/c/coreboot/+/80275/comment/5a188925_9ea27073 :
PS16, Line 337: MemoryInit
why don't we use 0xa4 for FSP_M MultiPhase entry and 0xa5 for exit?

File src/commonlib/include/commonlib/timestamp_serialized.h:

https://review.coreboot.org/c/coreboot/+/80275/comment/97709f8e_cd89abab :
PS16, Line 143: 972
why not 964 and 965 ?

File src/drivers/intel/fsp2_0/include/fsp/info_header.h:

https://review.coreboot.org/c/coreboot/+/80275/comment/f96adea1_09ab4e08 :
PS16, Line 41: fsp_smm_init_entry_offset
we don't need this, please mark reserved

File src/drivers/intel/fsp2_0/include/fsp/util.h:

https://review.coreboot.org/c/coreboot/+/80275/comment/d2eb1f30_a4286cd7 :
PS16, Line 83: };
             : 
             : struct fsp_multi_phase_get_number_of_phases_params {
             : 	uint32_t number_of_phases;
             : 	uint32_t phases_executed;
             : };
nit: move after line #58 ?

File src/drivers/intel/fsp2_0/memory_init.c:

https://review.coreboot.org/c/coreboot/+/80275/comment/79702d00_68c8c524 :
PS16, Line 278: fspm_return_value_handler
nit: why don't we create `fsp_return_value_handler` to address both FSP-M and S case now ?

https://review.coreboot.org/c/coreboot/+/80275/comment/4a1baeeb_fc8ec2a8 :
PS16, Line 433: 	fspm_multi_phase_init(hdr);
should we avoid calling into fspm_multi_phase_init() if FSP version is not 2.4?

File src/drivers/intel/fsp2_0/silicon_init.c:

https://review.coreboot.org/c/coreboot/+/80275/comment/2db67e9d_e3dfa5e4 :
PS16, Line 25: platform_fsp_silicon_multi_phase_init_cb
keep platform_fsp_silicon_multi_phase_init_cb and associated SoC file changes in a separate CL as base so, FSP 2.4 support additional can fit accordingly.

File util/cbfstool/eventlog.c:

https://review.coreboot.org/c/coreboot/+/80275/comment/ea26b73a_510ed0df :
PS16, Line 410: 		{POSTCODE_FSP_MULTI_PHASE_INIT_ENTRY, "FSP-M/S Multi Phase Init Enter"},
              : 		{POSTCODE_FSP_MULTI_PHASE_INIT_EXIT, "FPS-M/S Multi Phase Init Exit"},
as suggested, keep different post codes