Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44880 )
Change subject: security/intel/txt: Improve MTRR setup for GETSEC[ENTERACCS] ......................................................................
Patch Set 2:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44880/2/src/security/intel/txt/gets... File src/security/intel/txt/getsec_enteraccs.S:
https://review.coreboot.org/c/coreboot/+/44880/2/src/security/intel/txt/gets... PS2, Line 184: movd %eax, %xmm0 /* XMM0: Base address of next MTRR */
that only works if CONFIG_SSE is set
We're already using SSE registers in the code below. In fact, it's why I decided to use SSE registers in the first place.
https://review.coreboot.org/c/coreboot/+/44880/2/src/security/intel/txt/gets... PS2, Line 286: /* Backup stack pointer */ : movd %esp, %xmm0 : movd %ebp, %xmm1 See here