Attention is currently required from: Tarun Tuli, Subrata Banik.
Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70014 )
Change subject: soc/intel/{common, alderlake}: Add a config to support CSE sync in bootblock ......................................................................
soc/intel/{common, alderlake}: Add a config to support CSE sync in bootblock
Add SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK config to support CSE partition switching elarly in the boot flow.
Compile reset.c in bootblock to resolve a dependency in cse_lite.c.
Initialize HECI interface in bootblock if SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK is set.
TEST=Build and boot nirwen
Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com Change-Id: I16646c4cca773daa60f6add0f9c7349eb1e4edaa --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc 4 files changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/70014/1
diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 7f808ff..67f7b7e 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -17,6 +17,7 @@ bootblock-y += espi.c bootblock-y += p2sb.c bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c +bootblock-y += reset.c
romstage-y += espi.c romstage-y += meminit.c diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 712c128..f6966c0 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -9,6 +9,7 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci_ops.h> +#include <intelblocks/cse.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -127,4 +128,8 @@ pmc_gpe_init();
enable_rtc_upper_bank(); + + /* Initialize HECI interface */ + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK)) + cse_init(HECI1_BASE_ADDRESS); } diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 55a2b49..4a98a20 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -173,6 +173,14 @@ Mainboard user to select this Kconfig in order to capture pre-cpu reset boot performance telemetry data.
+config SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK + bool + default y + depends on SOC_INTEL_CSE_LITE_SKU + help + Use this option to switch to the correct partition based on vboot boot mode early + in the boot flow. + config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE bool default y diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index d5ea933..f05c35e 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,6 +1,8 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-$(CONFIG_SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK) += cse.c romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c +bootblock-$(CONFIG_SOC_INTEL_CSE_LITE_SYNC_IN_BOOTBLOCK) += cse_lite.c romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c