[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Lock down DMI3 PCI registers

[Jonathan Zhang (Code Review)]

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47448 )

Change subject: soc/intel/xeon_sp: Lock down DMI3 PCI registers
......................................................................

Patch Set 11:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47448/11//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47448/11//COMMIT_MSG@9 
PS11, Line 9: This is required for CbNT.
It is spelled as CBnT (Converged Bootguard and TXT).