[coreboot-gerrit] Change in coreboot[master]: cpu/intel/common: Extend FSB detection to cover TSC

[Patrick Georgi (Code Review)]

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31340 )

Change subject: cpu/intel/common: Extend FSB detection to cover TSC
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Patch Set 11:

(1 comment)

https://review.coreboot.org/c/coreboot/+/31340/11/src/cpu/intel/common/fsb.c 
File src/cpu/intel/common/fsb.c:

https://review.coreboot.org/c/coreboot/+/31340/11/src/cpu/intel/common/fsb.c... 
PS11, Line 50: 			*ratio = rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 24;
This rdmsr resets my getac p470 (family 06, model 0f, stepping 06), despite the claim of table 2-48 in docid #335592 that it should return information on scalable bus speed configuration.

Replacing it with *ratio = 1; fixes it for me. Even _adding_ that line after this (ie. the MSR value is disregarded), but keeping the rdmsr in returns to the reset loop.