Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37326 )
Change subject: AGESA,binaryPI: Split romstage_main() to BSP and AP parts ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37326/1/src/drivers/amd/agesa/romst... File src/drivers/amd/agesa/romstage.c:
https://review.coreboot.org/c/coreboot/+/37326/1/src/drivers/amd/agesa/romst... PS1, Line 56: if (initial_apic_id == 0) {
Good question. I believe this originates from multi-socket platforms and the intention was for only one core to execute this initialisation path. For each socket, one core would reports as boot_cpu() from what I remember.
Only core0 (BSC) on BSP (BKDG terminology) should have bit8 set (bsc bit) in lapic_base according to the fam 15h 00-0fh BKDG. It could be different on other families/variants or in actual silicon...