Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Julius Werner, Yu-Ping Wu, Jianjun Wang. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )
Change subject: coreboot tables: Add PCIe info to coreboot table ......................................................................
Patch Set 12:
(3 comments)
File src/commonlib/include/commonlib/coreboot_tables.h:
https://review.coreboot.org/c/coreboot/+/63251/comment/dfcc7cba_13c0e683 PS12, Line 151: lb_uint64_t ctrl_base; Sorry for my ignorance but what is this exactly? I know PCIe ECAM.
https://review.coreboot.org/c/coreboot/+/63251/comment/9ac4c280_2198ca1c PS12, Line 151: lb_uint64_t ctrl_base; /* Base address of PCIe controller */ : lb_uint64_t config_base; /* Base address of Config space */ : uint32_t config_size; : lb_uint64_t atu_base; maybe swap some things around so that each entry is aligned to it's entry size?
File src/lib/coreboot_table.c:
https://review.coreboot.org/c/coreboot/+/63251/comment/62608def_735cafc1 PS12, Line 36: __weak enum cb_err lb_fill_pcie(struct lb_pcie *pcie) : { : return CB_ERR; : } Does it make sense to have a better default? CONFIG_ECAM_MMCONF_BASE_ADDRESS is typically known at buildtime.