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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/55149
to look at the new patch set (#4).
Change subject: soc/amd/cezanne: Configure I2C Pad RX Select through devicetree ......................................................................
soc/amd/cezanne: Configure I2C Pad RX Select through devicetree
Some of the I2C buses are required to operate at different voltage level compared to other I2C buses eg. I2C bus to Google Security Chip (GSC) should be at 1.8V level. By default, all the I2C buses are initialized to operate at 3.3 V. Add support to configure I2C pad RX select through devicetree and update the concerned devicetree.
BUG=b:188538373 TEST=Build and boot to OS in Guybrush. Ensure that the communication with GSC is fine. Build Majolica mainboard.
Change-Id: I595a64736fdac0274abffb68c5e521302275b845 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/mainboard/amd/majolica/devicetree.cb M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chip.h M src/soc/amd/cezanne/i2c.c 4 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/55149/4