Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80270?usp=email )
Change subject: soc/amd/common/data_fabric/domain: introduce add_pci_cfg_resources ......................................................................
soc/amd/common/data_fabric/domain: introduce add_pci_cfg_resources
Since reporting the PCI ECAM MMCONF MMIO region and the IO ports for the legacy PCI config space access is needed on all AMD SoCs, implement a common add_pci_cfg_resources function that reports both and gets called from amd_pci_domain_read_resources and don't report those in the SoC- specific code any more. The only functional change is that on Genoa now the IO ports used for the legacy PCI config space access get reserved.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Ibbcc2aea4f25b6dc68fdf7f360e5a4ce53f6d850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80270 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/data_fabric/domain.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/root_complex.c M src/vendorcode/amd/opensil/genoa_poc/memmap.c 7 files changed, 8 insertions(+), 22 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 2586740..876f790 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -111,8 +111,6 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size;
- fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); - /* 0x0 - 0x9ffff */ ram_range(dev, (*idx)++, 0, 0xa0000);
@@ -134,8 +132,6 @@ */ ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
- mmconf_resource(dev, (*idx)++); - /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index 6573557..f5d7216 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -191,6 +191,12 @@ } }
+static void add_pci_cfg_resources(struct device *domain, unsigned long *idx) +{ + fixed_io_range_reserved(domain, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); + mmconf_resource(domain, (*idx)++); +} + void amd_pci_domain_read_resources(struct device *domain) { unsigned long idx = 0; @@ -203,6 +209,8 @@
/* Only add the SoC's DRAM memory map and fixed resources once */ if (domain->path.domain.domain == 0) { + add_pci_cfg_resources(domain, &idx); + read_soc_memmap_resources(domain, &idx); } } diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 37d189e..9d83f6f 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -126,8 +126,6 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size;
- fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); - /* 0x0 - 0x9ffff */ ram_range(dev, (*idx)++, 0, 0xa0000);
@@ -149,8 +147,6 @@ */ ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
- mmconf_resource(dev, (*idx)++); - /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 7291058..5561240 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -154,8 +154,6 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size;
- fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); - /* 0x0 - 0x9ffff */ ram_range(dev, (*idx)++, 0, 0xa0000);
@@ -177,8 +175,6 @@ */ ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
- mmconf_resource(dev, (*idx)++); - /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 3e61df1..1394b2c 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -126,8 +126,6 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size;
- fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); - /* 0x0 - 0x9ffff */ ram_range(dev, (*idx)++, 0, 0xa0000);
@@ -149,8 +147,6 @@ */ ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
- mmconf_resource(dev, (*idx)++); - /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index ffe4f66..1e702ab 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -111,8 +111,6 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size;
- fixed_io_range_reserved(dev, (*idx)++, PCI_IO_CONFIG_INDEX, PCI_IO_CONFIG_PORT_COUNT); - /* 0x0 - 0x9ffff */ ram_range(dev, (*idx)++, 0, 0xa0000);
@@ -132,8 +130,6 @@ * cbmem_top() accounts for low UMA and TSEG if they are used. */ ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable);
- mmconf_resource(dev, (*idx)++); - /* Reserve fixed IOMMU MMIO region */ mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE);
diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c index 1e633d9..39b27ec 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c +++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c @@ -114,8 +114,6 @@ if (mem_usable != top_mem) reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem);
- mmconf_resource(dev, (*idx)++); - // Check if we're done if (top_of_mem <= 0x100000000) return;