[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Disable MrcSafeConfig

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40106 )

Change subject: soc/intel/tigerlake: Disable MrcSafeConfig
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soc/intel/tigerlake: Disable MrcSafeConfig

This change disables MrcSafeConfig option during MRC training.
MrcSafeConfig was enabled as part of the early testing.
Now with FSP 2527, there is no need to set this config anymore.

BUG=b:150357377
BRANCH=master
TEST=build and boot ripto/volteer

Signed-off-by: Srinidhi N Kaushik 
Change-Id: I4e4069d83754aaf1e4885d6912ab2a6d506c5269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40106
Reviewed-by: Furquan Shaikh 
Reviewed-by: Wonkyu Kim 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/meminit.c
1 file changed, 0 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Srinidhi N Kaushik: Looks good to me, but someone else must approve
  Wonkyu Kim: Looks good to me, but someone else must approve

Objections:
  Nick Vaccaro: I would prefer that you didn't submit this

diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c
index 7823cfe..8664547 100644
--- a/src/soc/intel/tigerlake/meminit.c
+++ b/src/soc/intel/tigerlake/meminit.c
@@ -239,7 +239,6 @@
    /* LPDDR4x does not allow interleaved memory */
    mem_cfg->DqPinsInterleaved = 0;
    mem_cfg->ECT = board_cfg->ect;
-	mem_cfg->MrcSafeConfig = 0x1;

read_md_spd(info, &spd_data, &spd_len);
    mem_cfg->MemorySpdDataLen = spd_len;