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https://review.coreboot.org/c/coreboot/+/51455
to look at the new patch set (#4).
Change subject: mb/google/brya: brya0: Enable ADL_MAINBOARD_SUPPORTS_PCIEXP_HOTPLUG ......................................................................
mb/google/brya: brya0: Enable ADL_MAINBOARD_SUPPORTS_PCIEXP_HOTPLUG
This change select the Kconfig to pre-allocate the Intel-recommended bus and memory resources per-PCIe TBT root port for the brya0 mainboard.
TEST=snippet from dmesg logs shows the correct resources being allocated: PCI: 00:07.0 resource base 27fc00000 size 1c000000 align 20 gran 20 limit 29bbfffff flags 60181202 index 24 PCI: 00:07.0 resource base 83000000 size c200000 align 20 gran 20 limit 8f1fffff flags 60080202 index 20 PCI: 00:07.1 resource base 29bc00000 size 1c000000 align 20 gran 20 limit 2b7bfffff flags 60181202 index 24 PCI: 00:07.1 resource base a0000000 size c200000 align 20 gran 20 limit ac1fffff flags 60080202 index 20 PCI: 00:07.2 resource base 2b7c00000 size 1c000000 align 20 gran 20 limit 2d3bfffff flags 60181202 index 24 PCI: 00:07.2 resource base ac200000 size c200000 align 20 gran 20 limit b83fffff flags 60080202 index 20
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I6b520ae50f19a730263de7918594718f3b4b1c1a --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/51455/4