[coreboot-gerrit] [XL] Change in coreboot[main]: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat

[Jérémy Compostella (Code Review)]

Attention is currently required from: Bora Guvendik, Jamie Ryu, Jérémy Compostella, Paul Menzel, Zhixing Ma.

Hello Bora Guvendik, Cliff Huang, Jamie Ryu, Paul Menzel, Zhixing Ma, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/84564?usp=email

to look at the new patch set (#7).

The following approvals got outdated and were removed:
Code-Review+1 by Bora Guvendik, Code-Review+1 by Paul Menzel, Code-Review+1 by Zhixing Ma, Verified+1 by build bot (Jenkins)

Change subject: mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat
......................................................................

mb/intel/ptlrvp: Add Intel Panther Lake RVP as copy of google/fatcat

This commit introduces the Intel Panther Lake (PTL) Reference Validation
Platform (RVP) mainboard definition. It is aligned with the Google
Fatcat mainboard in the coreboot codebase, with the commit hash
e2ea7f22c6355d15515c049ca0dc4352173a0c01.

Intel's proprietary platform, commonly referred to as PTLRVP, and
Google's Fatcat mainboard share a considerable degree of similarity in
their design and capabilities. Nevertheless, Intel faces unique
challenges and requires specific board configurations that Google does
not. Consequently, there is a necessity for a specialized mainboard
tailored to Intel's individual needs.

To maintain consistency with the Fatcat board definition, the Chrome OS
Board Information (CBI) firmware configuration aligns with that of
Google Fatcat. If necessary, new bits will be appended, starting from
the end of the 32-bit firmware configuration field.

BUG=b:398880064
TEST=The Intel PTLRVP board successfully boots to the operating System.

Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d60
Signed-off-by: Jeremy Compostella 
---
A src/mainboard/intel/ptlrvp/Kconfig
A src/mainboard/intel/ptlrvp/Kconfig.name
A src/mainboard/intel/ptlrvp/Makefile.mk
A src/mainboard/intel/ptlrvp/board_info.txt
A src/mainboard/intel/ptlrvp/bootblock.c
A src/mainboard/intel/ptlrvp/chromeos.c
A src/mainboard/intel/ptlrvp/chromeos.fmd
A src/mainboard/intel/ptlrvp/dsdt.asl
A src/mainboard/intel/ptlrvp/ec.c
A src/mainboard/intel/ptlrvp/mainboard.c
A src/mainboard/intel/ptlrvp/romstage.c
A src/mainboard/intel/ptlrvp/smihandler.c
A src/mainboard/intel/ptlrvp/spd/Makefile.mk
A src/mainboard/intel/ptlrvp/variants/baseboard/include/baseboard/variants.h
A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk
A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/devicetree.cb
A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/ec.h
A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/include/baseboard/gpio.h
A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/memory.c
A src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c
A src/mainboard/intel/ptlrvp/variants/ptlrvp/Makefile.mk
A src/mainboard/intel/ptlrvp/variants/ptlrvp/fw_config.c
A src/mainboard/intel/ptlrvp/variants/ptlrvp/gpio.c
A src/mainboard/intel/ptlrvp/variants/ptlrvp/hda_verb.c
A src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/ec.h
A src/mainboard/intel/ptlrvp/variants/ptlrvp/include/variant/gpio.h
A src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
A src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/Makefile.mk
A src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/dram_id.generated.txt
A src/mainboard/intel/ptlrvp/variants/ptlrvp/memory/mem_parts_used.txt
A src/mainboard/intel/ptlrvp/variants/ptlrvp/overridetree.cb
A src/mainboard/intel/ptlrvp/variants/ptlrvp/variant.c
32 files changed, 3,070 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/84564/7