[coreboot-gerrit] Change in coreboot[master]: mb/ti/beaglebone: Initialize DDR3

[Sam Lewis (Code Review)]

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44387 )

Change subject: mb/ti/beaglebone: Initialize DDR3
......................................................................

mb/ti/beaglebone: Initialize DDR3

Adds initialisation of 512MB of DDR memory on the BBB to the romstage.
The parameters for the DDR peripherals are taken from U-Boot.

TEST: Booted from romstage into ramstage. Also successfully managed to
run the "ram_check" in lib.h.

Change-Id: I692bfd913c8217a78d073d19c5344c9bb40722a8
Signed-off-by: Sam Lewis 
---
M src/mainboard/ti/beaglebone-black/Kconfig
A src/mainboard/ti/beaglebone-black/ddr3.h
M src/mainboard/ti/beaglebone-black/romstage.c
3 files changed, 76 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/44387/1

diff --git a/src/mainboard/ti/beaglebone-black/Kconfig b/src/mainboard/ti/beaglebone-black/Kconfig
index a695942..5e60f25 100644
--- a/src/mainboard/ti/beaglebone-black/Kconfig
+++ b/src/mainboard/ti/beaglebone-black/Kconfig
@@ -24,7 +24,7 @@

config DRAM_SIZE_MB
    int
-	default 256
+	default 512

config UART_FOR_CONSOLE
    int
diff --git a/src/mainboard/ti/beaglebone-black/ddr3.h b/src/mainboard/ti/beaglebone-black/ddr3.h
new file mode 100644
index 0000000..5ed8f5e
--- /dev/null
+++ b/src/mainboard/ti/beaglebone-black/ddr3.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * Parameters to initialise the DDR3 memory on the Beaglebone Black
+ * Taken and adapted from U-Boot.
+ */
+
+#ifndef __MAINBOARD_TI_BEAGLEBONE_DDR3_H__
+#define __MAINBOARD_TI_BEAGLEBONE_DDR3_H__
+
+/* Micron MT41K256M16HA-125E */
+#define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
+#define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
+#define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
+#define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
+#define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
+#define MT41K256M16HA125E_EMIF_SDREF 0xC30
+#define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
+#define MT41K256M16HA125E_RATIO 0x80
+#define MT41K256M16HA125E_INVERT_CLKOUT 0x0
+#define MT41K256M16HA125E_RD_DQS 0x38
+#define MT41K256M16HA125E_WR_DQS 0x44
+#define MT41K256M16HA125E_PHY_WR_DATA 0x7D
+#define MT41K256M16HA125E_PHY_FIFO_WE 0x94
+#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
+
+#define EMIF_OCP_CONFIG_BEAGLEBONE_BLACK 0x00141414
+
+const struct ctrl_ioregs ioregs_bonelt = {
+	.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
+static const struct ddr_data ddr3_beagleblack_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_beagleblack_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+#endif
diff --git a/src/mainboard/ti/beaglebone-black/romstage.c b/src/mainboard/ti/beaglebone-black/romstage.c
index f1f68f9..bdaaaef 100644
--- a/src/mainboard/ti/beaglebone-black/romstage.c
+++ b/src/mainboard/ti/beaglebone-black/romstage.c
@@ -2,11 +2,20 @@

#include <program_loading.h>
 #include <console/console.h>
+#include <cbmem.h>
+
+#include <soc/ti/am335x/sdram.h>
+#include "ddr3.h"

void main(void)
 {
    console_init();
    printk(BIOS_INFO, "Hello from romstage.\n");

+	config_ddr(400, &ioregs_bonelt, &ddr3_beagleblack_data, &ddr3_beagleblack_cmd_ctrl_data,
+		   &ddr3_beagleblack_emif_reg_data, 0);
+
+	cbmem_initialize_empty();
+
    run_ramstage();
 }