PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37265 )
Change subject: soc/intel/cannonlake: Fix compilation ......................................................................
soc/intel/cannonlake: Fix compilation
change MicrocodeRegionLength to MicrocodeRegionSize as per coffeelake FsptUpd.h.
TEST= Build and boot test on coffeelake RVP.
Change-Id: Iebbf5c34e289870a4d7abdd49fd81e4db236051a Signed-off-by: Praveen Hodagatta Pranesh praveenx.hodagatta.pranesh@intel.com --- M src/soc/intel/cannonlake/bootblock/bootblock.c 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/37265/1
diff --git a/src/soc/intel/cannonlake/bootblock/bootblock.c b/src/soc/intel/cannonlake/bootblock/bootblock.c index 9f85397..6a6dd8b 100644 --- a/src/soc/intel/cannonlake/bootblock/bootblock.c +++ b/src/soc/intel/cannonlake/bootblock/bootblock.c @@ -39,10 +39,10 @@ * All SoC since Gen-4 has above mechanism in place to load microcode * even before hitting CPU reset vector. Hence skipping FSP-T loading * microcode after CPU reset by passing '0' value to - * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionLength. + * FSPT_UPD.MicrocodeRegionBase and FSPT_UPD.MicrocodeRegionSize. */ .MicrocodeRegionBase = 0, - .MicrocodeRegionLength = 0, + .MicrocodeRegionSize = 0, .CodeRegionBase = (uint32_t)(0x100000000ULL - CONFIG_ROM_SIZE), .CodeRegionSize = (uint32_t)CONFIG_ROM_SIZE,