[coreboot-gerrit] Change in coreboot[master]: riscv: add support for OpenSBI

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded a new patch set (#6) to the change originally created by Xiang Wang. ( https://review.coreboot.org/c/coreboot/+/32394 )

Change subject: riscv: add support for OpenSBI
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riscv: add support for OpenSBI

Call OpenSBI in M-Mode and use it to set up SBI and to lockdown the
platform. It will also jump to the specified payload when done.
This behaviour is similar to BL31 on aarch31.

The payload is 41KiB in size on qemu.

Tested on qemu-riscv:
Required to boot a kernel as OpenSBI's instruction emulation feature
is required on that virtual machine.

Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d
Signed-off-by: Xiang Wang 
Signed-off-by: Patrick Rudolph 
---
M src/arch/riscv/Kconfig
M src/arch/riscv/Makefile.inc
M src/arch/riscv/include/arch/boot.h
A src/arch/riscv/opensbi.c
M src/arch/riscv/payload.c
M src/arch/riscv/tables.c
6 files changed, 128 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32394/6