[coreboot-gerrit] Change in coreboot[master]: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35025 )

Change subject: soc/{amd, intel}: Make use of common postcar_enable_tseg_cache() API
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35025/6/src/soc/amd/picasso/romstag... 
File src/soc/amd/picasso/romstage.c:

https://review.coreboot.org/c/coreboot/+/35025/6/src/soc/amd/picasso/romstag... 
PS6, Line 89: 	if (CONFIG(SMM_TSEG))
Now that the call is in platform code, the conditional is unnecessary. In common code it would have been necessary to have it to handle AGESA (POSTCAR_STAGE=Y, SMM_ASEG=y) cases where we do not implement smm_region().