Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45571
to look at the new patch set (#4).
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
soc/intel/alderlake: Add GPIOs for Alder Lake SOC
Add definitions for the GPIO pins on Alder Lake LP, as well as GPIO IRQ routing information and supporting ACPI ASL.
For now, add the following 5 GPIO communities and 13 GPIO groups:
Comm. 0: GPP_B, GPP_T, GPP_A Comm. 1: GPP_S, GPP_H, GPP_D Comm. 2: GPD Comm. 4: GPP_C, GPP_F, GPP_E, GPP_HVMOS Comm. 5: GPP_R, GPP_SPI0
Change-Id: I77b9dcc46aceaf530e2054c9cacd7b026ebbb96b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/alderlake/Makefile.inc A src/soc/intel/alderlake/acpi/gpio.asl A src/soc/intel/alderlake/gpio.c A src/soc/intel/alderlake/include/soc/gpio.h A src/soc/intel/alderlake/include/soc/gpio_defs.h A src/soc/intel/alderlake/include/soc/gpio_soc_defs.h M src/soc/intel/alderlake/include/soc/pmc.h 7 files changed, 945 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45571/4