Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35186 )
Change subject: soc/intel/skylake: add some FSP SATA params ......................................................................
soc/intel/skylake: add some FSP SATA params
This adds SATA parameters for SpinUp, HotPlug and TestMode to the Skylake FSP 2.0 interface.
Signed-off-by: Michael Niewöhner foss@mniewoehner.de Change-Id: I7ba67879b78c2cb0fd0b0ce832140b213edd5884 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35186 Reviewed-by: Patrick Georgi pgeorgi@google.com Reviewed-by: Felix Singer felixsinger@posteo.net Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 10 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Felix Singer: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1313dc1..fee14d8 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -200,6 +200,8 @@ u8 SataSalpSupport; u8 SataPortsEnable[8]; u8 SataPortsDevSlp[8]; + u8 SataPortsSpinUp[8]; + u8 SataPortsHotPlug[8]; u8 SataSpeedLimit;
/* Audio related */ @@ -587,6 +589,9 @@
/* Enable/Disable Sata power optimization */ u8 SataPwrOptEnable; + + /* Enable/Disable Sata test mode */ + u8 SataTestMode; };
typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index de86936..d1d7d6f 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -283,6 +283,10 @@ sizeof(params->SataPortsEnable)); memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, sizeof(params->SataPortsDevSlp)); + memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, + sizeof(params->SataPortsHotPlug)); + memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, + sizeof(params->SataPortsSpinUp)); memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, @@ -369,6 +373,7 @@ tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; tconfig->PowerLimit4 = config->PowerLimit4; + tconfig->SataTestMode = config->SataTestMode; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree