Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75365?usp=email )
(
2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Limit SATA speed to Gen 2 ......................................................................
mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Limit SATA speed to Gen 2
Due to mainboard restrictions a SATA link at Gen 3 can cause issues as the margin is not big enough. Limit SATA speed to Gen 2 to achieve a more robust SATA connection.
Change-Id: Ifdea4542836b9c75b5507324fbb06b9566a6fe1d Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/75365 Reviewed-by: Jan Samek jan.samek@siemens.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb 3 files changed, 3 insertions(+), 0 deletions(-)
Approvals: Jan Samek: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index b515170..2b2c32d 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -70,6 +70,7 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" + register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 92bba65..15ca3f1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -70,6 +70,7 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" + register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 8223f68..3c907e3 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -41,6 +41,7 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" + register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED"