Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51730 )
Change subject: soc/mediatek/mt8192: Enlarge ROMSTAGE to 272K ......................................................................
soc/mediatek/mt8192: Enlarge ROMSTAGE to 272K
Enlarge ROMSTAGE from 256K to 272K for the upcoming change of MRC cache (CB:51620). To have more compact space usage, reduce BOOTBLOCK size from 64K to 60K (only 44K needed), and move starting address of DRAM blob (DRAM_INIT_CODE) to 0x210000 (64K-aligned).
BUG=b:170687062 TEST=emerge-asurada coreboot TEST=Hayato boots BRANCH=asurada
Cq-Depend: chrome-internal:3704751 Change-Id: I7aaf9faf048e0adcb3a7d856d40891762c9a6604 Signed-off-by: Yu-Ping Wu yupingso@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/51730 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Hung-Te Lin hungte@chromium.org --- M src/soc/mediatek/mt8192/include/soc/memlayout.ld 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index e84383b..150bfdd 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -40,13 +40,13 @@
SRAM_L2C_START(0x00200000) /* 4K reserved for BOOTROM until BOOTBLOCK is started */ - BOOTBLOCK(0x00201000, 64K) - OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00211000, 252K) + BOOTBLOCK(0x00201000, 60K) /* * The needed size can be obtained by: * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz */ - DRAM_INIT_CODE(0x00250000, 256K) + DRAM_INIT_CODE(0x00210000, 240K) + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x0024c000, 272K) PRERAM_CBFS_CACHE(0x00290000, 48K) PRERAM_CBMEM_CONSOLE(0x0029c000, 400K) SRAM_L2C_END(0x00300000)