Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36465 )
Change subject: soc/intel/{cnl,icl,skl}: Fix multiple whitespace issue ......................................................................
soc/intel/{cnl,icl,skl}: Fix multiple whitespace issue
Change-Id: I1e3dc1bd36c5de4e58eef6a3ba8ccbde28fba64b Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36465 Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/icelake/cpu.c M src/soc/intel/skylake/cpu.c 5 files changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index a3252c2..39433a2 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -90,7 +90,7 @@
/* Enable Bus Master and MMIO Space */ reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 |= PCI_COMMAND_MEMORY; + reg32 |= PCI_COMMAND_MEMORY; pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
/* Enable PWRM in PMC */ diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index c58b9ad..7f38279 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -399,7 +399,7 @@ * frequency is used. */ msr.hi = (3579545ULL << 32) / CTC_FREQ; - /* Set PM1 timer IO port and enable*/ + /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr); diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index aefcaa5..e95220b 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -72,7 +72,7 @@
/* Enable Bus Master and MMIO Space */ reg32 = pci_read_config32(PCH_DEV_PMC, PCI_COMMAND); - reg32 |= PCI_COMMAND_MEMORY; + reg32 |= PCI_COMMAND_MEMORY; pci_write_config32(PCH_DEV_PMC, PCI_COMMAND, reg32);
/* Enable PWRM in PMC */ diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 0ecccb9..a2d9f7a 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -127,7 +127,7 @@ * frequency is used. */ msr.hi = (3579545ULL << 32) / CTC_FREQ; - /* Set PM1 timer IO port and enable*/ + /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 63142b9..3ac1451 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -414,7 +414,7 @@ * frequency is used. */ msr.hi = (3579545ULL << 32) / CTC_FREQ; - /* Set PM1 timer IO port and enable*/ + /* Set PM1 timer IO port and enable */ msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); wrmsr(MSR_EMULATE_PM_TIMER, msr);