[coreboot-gerrit] [XS] Change in coreboot[main]: soc/amd/genoa/include/iomap: add missing I2C and I3C MMIO bases

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78897?usp=email )

Change subject: soc/amd/genoa/include/iomap: add missing I2C and I3C MMIO bases
......................................................................

soc/amd/genoa/include/iomap: add missing I2C and I3C MMIO bases

All base addresses of MMIO devices in the devicetree should also have
corresponding defines in iomap.h. PPR #55901 Rev 0.26 was used as a
reference.

Signed-off-by: Felix Held 
Change-Id: I0444e6cc0587b484a4a1ff49fa4b1540a24c8e80
---
M src/soc/amd/genoa/include/soc/iomap.h
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/78897/1

diff --git a/src/soc/amd/genoa/include/soc/iomap.h b/src/soc/amd/genoa/include/soc/iomap.h
index 076938e..5b767e3 100644
--- a/src/soc/amd/genoa/include/soc/iomap.h
+++ b/src/soc/amd/genoa/include/soc/iomap.h
@@ -18,9 +18,16 @@
 #define APU_I2C1_BASE			0xfedc3000
 #define APU_I2C2_BASE			0xfedc4000
 #define APU_I2C3_BASE			0xfedc5000
+#define APU_I2C4_BASE			0xfedc6000
+#define APU_I2C5_BASE			0xfedcb000

#define APU_UART0_BASE			0xfedc9000
 #define APU_UART1_BASE			0xfedca000
 #define APU_UART2_BASE			0xfedce000

+#define APU_I3C0_BASE			0xfedd2000
+#define APU_I3C1_BASE			0xfedd3000
+#define APU_I3C2_BASE			0xfedd4000
+#define APU_I3C3_BASE			0xfedd6000
+
 #endif /* AMD_GENOA_IOMAP_H */