Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... File src/soc/intel/alderlake/gpio.c:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/gpi... PS2, Line 66: static const struct pad_community adl_communities[] = {
We'll see. […]
yes, i had the same plan, even my code was ready in that way but when we upstream we shall do in same way
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
and don't expect even FSP also does those programming as well.
Sorry, I can't parse that. Do you mean "FSP does not program these GPIOs" (vGPIO for example?) If yes, then this is untrue - for CNL as well as ICL, TGL and probably ADL.
if its only SOC GPIO which doesn't need to have any board configuration point like JTAG, CPU, SPI0 etc. is meant to only set to default and BIOS (coreboot or FSP) don't expect to program those. Anything we wish to program should have been documented in EDS. If you have seen other cases it might be a bug and better to follow up that.
We have also seen some cases in past platform where FSP unnecessary program new GPIO in Native mode (this is only what FSP can do) and coreboot want to use that as GPIO mode hence we have possibly guard all such NF programming GPIO inside FSP using UPD to ensure it doesn't override coreboot GPIO pad configuration.
Any GPIO with PIN MUX feature FSP has UPD to ignore FSP to program, for example: if I2C3 doesn't have device attached on board we make the UPD disable
Well, FSP in some cases does nothing more than setting NF1, which coreboot can, too.
Yes, FSP can only set GPIO to NF but my point is if board design don't like to use that GPIO in NF then FSP shouldn't do that override even, hence we have guarded all NF inside FSP using possible UPD to avoid overrides