Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/29023
Change subject: riscv: add support smp_pause / smp_resume ......................................................................
riscv: add support smp_pause / smp_resume
See https://doc.coreboot.org/arch/riscv/ we know that we need to execute smp_pause at the start of each stage and smp_resume at the end of each stage.
Change-Id: I6f8159637bfb15f54f0abeb335de2ba6e9cf82fb Signed-off-by: Xiang Wang wxjstz@126.com --- M src/arch/riscv/Kconfig A src/arch/riscv/include/arch/smp/smp.h M src/arch/riscv/include/mcall.h 3 files changed, 66 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29023/1
diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig index 2d53f42..96179a5 100644 --- a/src/arch/riscv/Kconfig +++ b/src/arch/riscv/Kconfig @@ -32,3 +32,7 @@ config RISCV_USE_ARCH_TIMER bool default n + +config RISCV_HART_NUM + int + diff --git a/src/arch/riscv/include/arch/smp/smp.h b/src/arch/riscv/include/arch/smp/smp.h new file mode 100644 index 0000000..7431142 --- /dev/null +++ b/src/arch/riscv/include/arch/smp/smp.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 HardenedLinux. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _RISCV_SMP_H +#define _RISCV_SMP_H + +#include <arch/encoding.h> +#include <arch/smp/spinlock.h> +#include <mcall.h> +#include <commonlib/compiler.h> + +void set_msip(int hartid, int val); + +static inline void smp_pause(void) +{ + if (read_csr(mhartid) == 0) + return; + clear_csr(mstatus, MSTATUS_MIE); + write_csr(mie, MIP_MSIP); + do { + barrier(); + __asm__ volatile ("wfi"); + } while ((read_csr(mip) & MIP_MSIP) == 0); + set_msip(read_csr(mhartid), 0); + HLS()->entry.fn(HLS()->entry.arg); +} + +static inline void smp_resume(void (*fn)(void *), void *arg) +{ + int hartid = read_csr(mhartid); + for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++) { + OTHER_HLS(i)->entry.fn = fn; + OTHER_HLS(i)->entry.arg = arg; + } + + for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++) + if (i != hartid) + set_msip(i, 1); + + HLS()->entry.fn(HLS()->entry.arg); +} + +#endif + diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index d1e414a..3e559f7 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -18,7 +18,7 @@
// NOTE: this is the size of hls_t below. A static_assert would be // nice to have. -#define HLS_SIZE 64 +#define HLS_SIZE 80
/* We save 37 registers, currently. */ #define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8) @@ -35,6 +35,10 @@ unsigned long sbi_private_data; } sbi_device_message;
+struct blocker { + void *arg; + void (*fn)(void *arg); +};
typedef struct { sbi_device_message *device_request_queue_head; @@ -46,6 +50,7 @@ int ipi_pending; uint64_t *timecmp; uint64_t *time; + struct blocker entry; } hls_t;
#define MACHINE_STACK_TOP() ({ \