[coreboot-gerrit] Change in coreboot[master]: mainboard/hatch: Enable TetonGlacierMode on Puff

[Edward O'Callaghan (Code Review)]

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38846 )

Change subject: mainboard/hatch: Enable TetonGlacierMode on Puff
......................................................................

mainboard/hatch: Enable TetonGlacierMode on Puff

Allow for reconfiguring the PCIe lanes at runtime.

BUG=b:149171631
BRANCH=none
TEST=none

Change-Id: Id9a72161494db6a4da4abd3302b06df7c70634ab
Signed-off-by: Edward O'Callaghan 
---
M src/mainboard/google/hatch/variants/puff/overridetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38846/1

diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb
index 4ffbfed..09c109a 100644
--- a/src/mainboard/google/hatch/variants/puff/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb
@@ -2,6 +2,9 @@
    # Enable heci communication
    register "HeciEnabled" = "1"

+	# Auto-switch between X4 NVMe and X2 NVMe.
+	register "TetonGlacierMode" = "1"
+
    register "SerialIoDevMode" = "{
    	[PchSerialIoIndexI2C0]  = PchSerialIoDisabled,
    	[PchSerialIoIndexI2C1]  = PchSerialIoDisabled,
@@ -281,6 +284,7 @@
    		end
    	end # FSP requires func0 be enabled.
    	device pci 1c.6 on  end # RTL8111H Ethernet NIC (becomes RP1).
+		device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
    	device pci 1e.3 off end # GSPI #1
    end