Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38691 )
Change subject: soc/amd/picasso: Enable cache in bootblock ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... File src/soc/amd/picasso/bootblock/bootblock.c:
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... PS2, Line 66: get_free_var_mtrr() Does the system always come out of reset with cleared variable MTRR's? On Intel systems those are always cleared before setting MTRR_DEF_TYPE_MSR and setting up CAR and bootblock/romstage caching.
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... PS2, Line 74: set_var_mtrr You might want to cover .earlyram.data with a variable MTRR too.
https://review.coreboot.org/c/coreboot/+/38691/2/src/soc/amd/picasso/bootblo... PS2, Line 84: set_caching(); Do this first? It does not seem to depend on the previous ones and should provide a speed up.