Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34424 )
Change subject: soc/amd/picasso: Update northbridge ......................................................................
Patch Set 16:
(3 comments)
https://review.coreboot.org/c/coreboot/+/34424/15/src/soc/amd/picasso/northb... File src/soc/amd/picasso/northbridge.c:
https://review.coreboot.org/c/coreboot/+/34424/15/src/soc/amd/picasso/northb... PS15, Line 59: hybrid romstage
Is the stack here?
Currently the pre-ramstage stack(s) are contained within the 1st stage's region.
https://review.coreboot.org/c/coreboot/+/34424/15/src/soc/amd/picasso/northb... PS15, Line 63: DRAM consumed for hybrid romstage
This is said twice here. […]
I don't see it as duplicate. The first one was on line 59? That's the region above 1MB, but this is the stage itself. I'll try to clarify though.
https://review.coreboot.org/c/coreboot/+/34424/15/src/soc/amd/picasso/northb... PS15, Line 144: .read_resources = read_resources,
Would you not want this to be part of a chip operation instead of a __pci_driver? It avoids needing […]
Oops, missed considering this one before repushing.