[coreboot-gerrit] Change in coreboot[master]: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37197 )

Change subject: drivers/amd/agesa/romstage: Only mark cbmem as UC if needed
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Patch Set 12:

I have recently noticed that after apu2 migration to postcar the MTRRs became inconsistent across all cores. The APs have an additional UC entry probably for cbmem?, which stays programmed up to the CPU init in ramstage. Since the postcar frame is built only from WB entries, the BSP has one entry less than APs which causes this inconsistence. Would this patch resolve this issue? Or is this something different?

Anyway I will test this.