[coreboot-gerrit] Change in coreboot[master]: [UNTESTED] soc/intel/apl: enable ACPI CPPC entries

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47542 )

Change subject: [UNTESTED] soc/intel/apl: enable ACPI CPPC entries
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Patch Set 10:
> Patch Set 10:
>
> No entries are generated on google/ampton with this patch due to it not supporting Speedshift (cpuid_eax(6) & CPUID_6_EAX_ISST == 0) and I don't have another APL/GLK device which does support it to test

Thanks for testing anyways :-)