Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22980
Change subject: sb/intel/i82801ix: Use the common ACPI pirq generator ......................................................................
sb/intel/i82801ix: Use the common ACPI pirq generator
For this to work the northbridge and lpc bridge device need acpi_name functions.
This also needs DEFAULT_RCBA being configured in Kconfig.
Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- D src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl D src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl D src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl M src/northbridge/intel/gm45/acpi/hostbridge.asl M src/northbridge/intel/gm45/northbridge.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c 8 files changed, 32 insertions(+), 245 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/22980/1
diff --git a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl deleted file mode 100644 index aefdf94..0000000 --- a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * gm45 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Onboard GbE - Package() { 0x0019ffff, 0, 0, 16 }, - // USB and EHCI 0:1a.x - Package() { 0x001affff, 0, 0, 16 }, - Package() { 0x001affff, 1, 0, 17 }, - Package() { 0x001affff, 2, 0, 18 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 16 }, - Package() { 0x001dffff, 1, 0, 17 }, - Package() { 0x001dffff, 2, 0, 18 }, - // LPC bridge sub devices 0:1f.x - Package() { 0x001fffff, 1, 0, 17 }, - Package() { 0x001fffff, 2, 0, 18 } - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // Onboard GbE - Package() { 0x0019ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // USB and EHCI 0:1a.x - Package() { 0x001affff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001affff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001affff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001dffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001dffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - // LPC bridge sub devices 0:1f.x - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKC, 0 } - }) - } -} diff --git a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl deleted file mode 100644 index aefdf94..0000000 --- a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * gm45 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Onboard GbE - Package() { 0x0019ffff, 0, 0, 16 }, - // USB and EHCI 0:1a.x - Package() { 0x001affff, 0, 0, 16 }, - Package() { 0x001affff, 1, 0, 17 }, - Package() { 0x001affff, 2, 0, 18 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 16 }, - Package() { 0x001dffff, 1, 0, 17 }, - Package() { 0x001dffff, 2, 0, 18 }, - // LPC bridge sub devices 0:1f.x - Package() { 0x001fffff, 1, 0, 17 }, - Package() { 0x001fffff, 2, 0, 18 } - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // Onboard GbE - Package() { 0x0019ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // USB and EHCI 0:1a.x - Package() { 0x001affff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001affff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001affff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, _SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001dffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001dffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - // LPC bridge sub devices 0:1f.x - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKC, 0 } - }) - } -} diff --git a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl deleted file mode 100644 index 4a9ede8..0000000 --- a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * gm45 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // USB and EHCI 0:1a.x - Package() { 0x001affff, 0, 0, 16 }, - Package() { 0x001affff, 1, 0, 17 }, - Package() { 0x001affff, 2, 0, 18 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 16 }, - Package() { 0x001dffff, 1, 0, 17 }, - Package() { 0x001dffff, 2, 0, 18 }, - // FIXME - // CardBus/IEEE1394 0:1e.2, 0:1e.3 - // Package() { 0x001effff, 0, 0, 22 }, - // Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 16 }, - Package() { 0x001fffff, 1, 0, 17 }, - Package() { 0x001fffff, 2, 0, 18 } - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // USB and EHCI 0:1a.x - Package() { 0x001affff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001affff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001affff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001dffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001dffff, 2, _SB.PCI0.LPCB.LNKC, 0 }, - // FIXME - // CardBus/IEEE1394 0:1e.2, 0:1e.3 - // Package() { 0x001effff, 0, _SB.PCI0.LPCB.LNKG, 0 }, - // Package() { 0x001effff, 1, _SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, _SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 1, _SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 2, _SB.PCI0.LPCB.LNKC, 0 } - }) - } -} diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index c674df5..afa7a61 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -228,6 +228,3 @@
Return (MCRS) } - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/gm45_pci_irqs.asl" diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 8215979..431d98d 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -186,6 +186,22 @@ pci_write_config32(dev, PCI_COMMAND, reg32); }
+static const char *northbridge_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0, 0): + return "MCHC"; + } + + return NULL; +} + static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, @@ -195,6 +211,7 @@ .ops_pci_bus = pci_bus_default_ops, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_name = northbridge_acpi_name, };
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 6879bce..2752e7a 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -18,6 +18,7 @@ bool select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET @@ -33,6 +34,10 @@ hex default 0xfef00000
+config DEFAULT_RCBA + hex + default 0xfed1c000 + config HPET_MIN_TICKS hex default 0x80 diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 38dfa38..90e8953 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -26,9 +26,9 @@
#define DEFAULT_TBAR ((u8 *)0xfed1b000) #ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#define DEFAULT_RCBA ((u8 *)CONFIG_DEFAULT_RCBA) #else -#define DEFAULT_RCBA 0xfed1c000 +#define DEFAULT_RCBA CONFIG_DEFAULT_RCBA #endif
#if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index bc45b9d..dc582c9 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -34,6 +34,7 @@ #include "nvs.h" #include <southbridge/intel/common/pciehp.h> #include <drivers/intel/gma/i915.h> +#include <southbridge/intel/common/acpi_pirq_gen.h>
#define NMI_OFF 0
@@ -558,12 +559,18 @@ } }
+static const char *lpc_acpi_name(const struct device *dev) +{ + return "LPCB"; +} + static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info;
intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); + intel_acpi_gen_def_acpi_pirq(device); }
static struct pci_operations pci_ops = { @@ -577,6 +584,7 @@ .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_name = lpc_acpi_name, .init = lpc_init, .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops,