[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add GPIOs for Alder Lake SOC

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )

Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC
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Patch Set 8:

(1 comment)

File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:

https://review.coreboot.org/c/coreboot/+/45571/comment/efafc502_067ccddc 
PS8, Line 10: /* GPIO COMM 0 */
            : #define GPP_B			0x0
            : #define GPP_T			0x1
            : #define GPP_A			0x2
            : /* GPIO COMM 1 */
            : #define GPP_S			0x3
            : #define GPP_H			0x4
            : #define GPP_D			0x5
            : /* GPIO COMM 2 */
            : #define GPD			0x6
            : /* GPIO COMM 4 */
            : #define GPP_C			0x7
            : #define GPP_F			0x8
            : #define GPP_HVMOS		0x9
            : #define GPP_E			0xA
            : /* GPIO COMM 5 */
            : #define GPP_R			0xB
            : #define GPP_SPI0		0xC
            :
> GPP_* values here must match what is in MISCCFG registers. See section 27.1. […]

Thanks Furquan for the details, do you want me to fix this code ?