[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/apl: enable lpc at bootblock

[Thomas Heijligen (Code Review)]

Hello Nico Huber,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/31371

to review the following change.

Change subject: soc/intel/apl: enable lpc at bootblock
......................................................................

soc/intel/apl: enable lpc at bootblock

Serial console can be attached to lpc bus. Enable it for early debug

Change-Id: Ib3d09e4eb23655825b7603f49f0bad31116ac6e1
Signed-off-by: Nico Huber 
Signed-off-by: Thomas Heijligen 
---
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/chip.h
M src/soc/intel/apollolake/lpc.c
M src/soc/intel/common/block/lpc/lpc_lib.c
4 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31371/1

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index cf3e839..e0217ef 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/fast_spi.h>
+#include <intelblocks/lpc_lib.h>
 #include <intelblocks/p2sb.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
@@ -120,4 +121,6 @@
    	paging_set_default_pat();
    	paging_enable_for_car("pdpt", "pt");
    }
+
+	pch_enable_lpc();
 }
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index b8f9f8c..2f25a3b 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -44,6 +44,9 @@
    /* Common structure containing soc config data required by common code*/
    struct soc_intel_common_config common_soc_config;

+	/* Generic i/o decode ranges routed to LPC */
+	uint32_t lpc_gen_dec[4];
+
    /*
     * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
     * four CLKREQ inputs, but six root ports. Root ports without an
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index a20b82a..ffa4cf5 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -42,6 +42,18 @@
    return apl_lpc_fixed_mmio_ranges;
 }

+void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
+{
+	const struct soc_intel_apollolake_config *const config = dev->chip_info;
+
+	if (!config) {
+		memset(gen_io_dec, 0x00, sizeof(config->lpc_gen_dec));
+		return;
+	}
+
+	memcpy(gen_io_dec, config->lpc_gen_dec, sizeof(config->lpc_gen_dec));
+}
+
 static const struct pad_config lpc_gpios[] = {
 #if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
 #if !IS_ENABLED(CONFIG_SOC_ESPI)
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index fb50b74..d584d2c 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -24,6 +24,9 @@
 #include <lib.h>
 #include "lpc_def.h"
 #include <soc/pci_devs.h>
+#include <stdint.h>
+
+__weak void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) {}

uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables)
 {