[coreboot-gerrit] Change in coreboot[master]: [WIP] mb/google/guybrush: add DXIO and DDI descriptors

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51957 )

Change subject: [WIP] mb/google/guybrush: add DXIO and DDI descriptors
......................................................................

[WIP] mb/google/guybrush: add DXIO and DDI descriptors

Signed-off-by: Felix Held 
Change-Id: Ic8a4349315f8759c79dc6b087b2a933c307cd573
---
M src/mainboard/google/guybrush/port_descriptors.c
1 file changed, 59 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/51957/1

diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c
index d407fe9..f3aa6b7 100644
--- a/src/mainboard/google/guybrush/port_descriptors.c
+++ b/src/mainboard/google/guybrush/port_descriptors.c
@@ -4,9 +4,68 @@
 #include <types.h>

static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
+	{ /* WLAN */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_logical_lane = 0,
+		.end_logical_lane = 0,
+		.device_number = 0,
+		.function_number = 0,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ0,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* SD */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_logical_lane = 1,
+		.end_logical_lane = 1,
+		.device_number = 0,
+		.function_number = 0,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ1,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* WWAN */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_logical_lane = 2,
+		.end_logical_lane = 2,
+		.device_number = 0,
+		.function_number = 0,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ2,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* NVME */
+		.port_present = true,
+		.engine_type = PCIE_ENGINE,
+		.start_logical_lane = 4,
+		.end_logical_lane = 7,
+		.device_number = 0,
+		.function_number = 0,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ3,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	}
 };

static const fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = {
+	{ /* DDI0 - DP */
+		.connector_type = DDI_DP,
+		.aux_index = DDI_AUX1,
+		.hdp_index = DDI_HDP1
+	},
+	{ /* DDI1 - eDP */
+		.connector_type = DDI_HDMI,
+		.aux_index = DDI_AUX2,
+		.hdp_index = DDI_HDP2
+	},
+	{ /* DDI2 - DP */
+		.connector_type = DDI_DP,
+		.aux_index = DDI_AUX3,
+		.hdp_index = DDI_HDP3,
+	}
 };

void mainboard_get_dxio_ddi_descriptors(