[coreboot-gerrit] Change in coreboot[master]: mb/google/guybrush: Configure eSPI GPIOs in verstage

[Mathew King (Code Review)]

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51295 )

Change subject: mb/google/guybrush: Configure eSPI GPIOs in verstage
......................................................................

mb/google/guybrush: Configure eSPI GPIOs in verstage

BUG=b:181961514
TEST=builds

Signed-off-by: Mathew King 
Change-Id: I0d22de977f09cbf46b28243d9f0c1e9a36e1398f
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
1 file changed, 11 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/51295/1

diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index 270cc86..7176022 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -108,16 +108,7 @@
    /* CLK_REQ0_L */
    PAD_NF(GPIO_92, CLK_REQ0_L, PULL_NONE),
    /* GPIO_93 - GPIO_103: Not available */
-	/* ESPI1_DATA0 */
-	PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
-	/* ESPI1_DATA1 */
-	PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE),
-	/* ESPI1_DATA2 */
-	PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
-	/* ESPI1_DATA3 */
-	PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
-	/* ESPI_ALERT_L */
-	PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
+	/* GPIO_104 - GPIO_108: eSPI configured in verstage */
    /* RAM_ID_0 / DEV_BEEP_EN */
    PAD_GPI(GPIO_109, PULL_NONE),
    /* GPIO_110 - GPIO_112: Not available */
@@ -170,7 +161,16 @@

/* Early GPIO configuration in verstage */
 static const struct soc_amd_gpio verstage_gpio_table[] = {
-	/* TODO: Fill verstage gpio configuration */
+	/* ESPI1_DATA0 */
+	PAD_NF(GPIO_104, SPI2_DO_ESPI2_D0, PULL_NONE),
+	/* ESPI1_DATA1 */
+	PAD_NF(GPIO_105, SPI2_DI_ESPI2_D1, PULL_NONE),
+	/* ESPI1_DATA2 */
+	PAD_NF(GPIO_106, EMMC_SPI2_WP_L_ESPI2_D2, PULL_NONE),
+	/* ESPI1_DATA3 */
+	PAD_NF(GPIO_107, SPI2_HOLD_L_ESPI2_D3, PULL_NONE),
+	/* ESPI_ALERT_L */
+	PAD_NF(GPIO_108, ESPI_ALERT_D1, PULL_NONE),
 };

/* GPIO configuration for sleep */