Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86136?usp=email )
Change subject: mb/starlabs/byte_adl: Correct MODEM_CLKREQ configuration ......................................................................
mb/starlabs/byte_adl: Correct MODEM_CLKREQ configuration
This GPIO is used as MODEM_CLKREQ, which is Native Function 1. Adjust the configuration accordingly.
Change-Id: If9db29df2a0da71885556a75abcb1da1508a9308 Signed-off-by: Sean Rhodes sean@starlabs.systems Reviewed-on: https://review.coreboot.org/c/coreboot/+/86136 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Matt DeVillier matt.devillier@gmail.com --- M src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c index 4a6f38e..ae814f0 100644 --- a/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c +++ b/src/mainboard/starlabs/byte_adl/variants/mk_ii/gpio.c @@ -298,8 +298,8 @@ PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), /* F4: CNV RF Reset */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), - /* F5: Not used MODEM_CLKREQ */ - PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* F5: MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* F6: CNV PA Blanking */ PAD_NC(GPP_F6, NONE), /* F7: TBT LSX VCCIO Weak Internal PD 20K