Attention is currently required from: Jamie Chen, Tim Wawrzynczak, Karthik Ramasubramanian. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63675 )
Change subject: soc/intel/jasperlake: Add a workaround for cnvi ......................................................................
Patch Set 3:
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63675/comment/53b5a48e_7a90b4e7 PS3, Line 7: soc/intel/jasperlake: Add a workaround for cnvi Maybe:
CNVI: Enable fewer wakeups to decrease high SoC power consumption
https://review.coreboot.org/c/coreboot/+/63675/comment/b7d5ced2_7235da20 PS3, Line 9: add a workaround to mitigate : the higher SoC power consumption in S0iX … work around higher SoC power consumption in S0iX, when CNVI has background activity.
https://review.coreboot.org/c/coreboot/+/63675/comment/721c5043_dc3e1f8a PS3, Line 15: Those settings are correct. Please add the exact power consumption values.
File src/soc/intel/jasperlake/chip.h:
https://review.coreboot.org/c/coreboot/+/63675/comment/420fec1d_b7a83e22 PS3, Line 430: AC9560(JfP2) Please add a space before the (.
https://review.coreboot.org/c/coreboot/+/63675/comment/15ba647e_34e98e92 PS3, Line 430: chipsets : Please remove the space before the colon.
https://review.coreboot.org/c/coreboot/+/63675/comment/74e279ef_103df6ac PS3, Line 431: AX201(HrP2) Ditto.
https://review.coreboot.org/c/coreboot/+/63675/comment/8ae36e16_14c7827c PS3, Line 433: 1: Enabled(fewer wakes, lower power); 0: Disabled(more wakes, higher power) Please use true/false, and add a space before the (.
https://review.coreboot.org/c/coreboot/+/63675/comment/30458348_31c6ed3c PS3, Line 435: bool cnvi_s0ix_wa; Add “power usage” or something similar to the name?